fast_sub.vhd

来自「实现4位加减乘除的alu」· VHDL 代码 · 共 27 行

--快速减法
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY fast_sub IS
	GENERIC(N	:INTEGER:= 4);
	PORT( A,B	:IN 	STD_LOGIC_VECTOR(N-1 downto 0);
		  bin	:IN 	STD_LOGIC;
		  Diff	:OUT 	STD_LOGIC_VECTOR(N-1 downto 0);
		  bout	:OUT 	STD_LOGIC);
END fast_sub;
		
ARCHITECTURE Behavior OF fast_sub IS
COMPONENT fast_add IS
	GENERIC(N:	INTEGER	:=	4);
    PORT(A		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		 B		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Cin	:IN		STD_LOGIC;
         Sum	:OUT	STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Cout	:OUT	STD_LOGIC);
END COMPONENT;
SIGNAL bout_Buf		:STD_LOGIC;
BEGIN
	add:fast_add GENERIC MAP(4)
		PORT MAP(A,NOT B,NOT bin,diff,bout_Buf);	
		bout	<= NOT bout_Buf;	--输出借位
END Behavior;