alu.fit.eqn

实现4位加减乘除的alu

D1L33 = D1_reg[1] & !G3_unreg_res_node[4] & !D1_reg[0] # !D1_reg[1] & D1_reg[0] & G2_unreg_res_node[3];


--J3_cs_buffer[3] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC3_C3
--operation mode is arithmetic

J3_cs_buffer[3] = C1_reg[5] $ C1_regM[2] $ J3_cout[2];

--J3_cout[3] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] at LC3_C3
--operation mode is arithmetic

J3_cout[3] = CARRY(C1_reg[5] & (J3_cout[2] # !C1_regM[2]) # !C1_reg[5] & !C1_regM[2] & J3_cout[2]);


--C1L63 is fast_div:div|reg~1125 at LC8_C2
--operation mode is normal

C1L63 = J3_cs_buffer[3] & !C1L9 & C1_reg[5] # !J3_cs_buffer[3] & (C1L9 # C1_reg[5]);


--D1L43 is booth_mul:mul|reg~2860 at LC6_B13
--operation mode is normal

D1L43 = D1L33 # D1_reg[8] & (D1_reg[0] $ !D1_reg[1]);


--J3_cs_buffer[2] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC2_C3
--operation mode is arithmetic

J3_cs_buffer[2] = C1_reg[4] $ C1_regM[1] $ J3_cout[1];

--J3_cout[2] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] at LC2_C3
--operation mode is arithmetic

J3_cout[2] = CARRY(C1_reg[4] & (J3_cout[1] # !C1_regM[1]) # !C1_reg[4] & !C1_regM[1] & J3_cout[1]);


--C1L73 is fast_div:div|reg~1127 at LC5_C3
--operation mode is normal

C1L73 = J3_cs_buffer[2] & !C1L9 & C1_reg[4] # !J3_cs_buffer[2] & (C1L9 # C1_reg[4]);


--J6_cs_buffer[2] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC4_B16
--operation mode is arithmetic

J6_cs_buffer[2] = D1_reg[7] $ D1_regM[2] $ J6_cout[1];

--J6_cout[2] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] at LC4_B16
--operation mode is arithmetic

J6_cout[2] = CARRY(D1_reg[7] & (D1_regM[2] # J6_cout[1]) # !D1_reg[7] & D1_regM[2] & J6_cout[1]);


--J9_cs_buffer[3] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC7_B15
--operation mode is arithmetic

J9_cs_buffer[3] = D1_reg[7] $ D1_regM[2] $ J9_cout[2];

--J9_cout[3] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] at LC7_B15
--operation mode is arithmetic

J9_cout[3] = CARRY(D1_reg[7] & (J9_cout[2] # !D1_regM[2]) # !D1_reg[7] & !D1_regM[2] & J9_cout[2]);


--D1L53 is booth_mul:mul|reg~2862 at LC8_B13
--operation mode is normal

D1L53 = D1_reg[1] & !J9_cs_buffer[3] & !D1_reg[0] # !D1_reg[1] & D1_reg[0] & J6_cs_buffer[2];


--D1L63 is booth_mul:mul|reg~2863 at LC1_B13
--operation mode is normal

D1L63 = D1L53 # D1_reg[7] & (D1_reg[0] $ !D1_reg[1]);


--J3_cs_buffer[1] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC1_C3
--operation mode is arithmetic

J3_cs_buffer[1] = C1_regM[0] $ C1_reg[3];

--J3_cout[1] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] at LC1_C3
--operation mode is arithmetic

J3_cout[1] = CARRY(C1_reg[3] # !C1_regM[0]);


--C1L83 is fast_div:div|reg~1129 at LC7_C5
--operation mode is normal

C1L83 = C1L9 & J3_cs_buffer[1] # !C1L9 & C1_reg[3];


--J6_cs_buffer[1] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC3_B16
--operation mode is arithmetic

J6_cs_buffer[1] = D1_reg[6] $ D1_regM[1] $ J6_cout[0];

--J6_cout[1] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] at LC3_B16
--operation mode is arithmetic

J6_cout[1] = CARRY(D1_reg[6] & (D1_regM[1] # J6_cout[0]) # !D1_reg[6] & D1_regM[1] & J6_cout[0]);


--J9_cs_buffer[2] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC6_B15
--operation mode is arithmetic

J9_cs_buffer[2] = D1_reg[6] $ D1_regM[1] $ J9_cout[1];

--J9_cout[2] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] at LC6_B15
--operation mode is arithmetic

J9_cout[2] = CARRY(D1_reg[6] & (J9_cout[1] # !D1_regM[1]) # !D1_reg[6] & !D1_regM[1] & J9_cout[1]);


--D1L73 is booth_mul:mul|reg~2865 at LC6_B16
--operation mode is normal

D1L73 = D1_reg[1] & !J9_cs_buffer[2] & !D1_reg[0] # !D1_reg[1] & D1_reg[0] & J6_cs_buffer[1];


--D1L83 is booth_mul:mul|reg~2866 at LC8_B16
--operation mode is normal

D1L83 = D1L73 # D1_reg[6] & (D1_reg[0] $ !D1_reg[1]);


--J6_cs_buffer[0] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] at LC2_B16
--operation mode is arithmetic

J6_cs_buffer[0] = D1_regM[0] $ D1_reg[5];

--J6_cout[0] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] at LC2_B16
--operation mode is arithmetic

J6_cout[0] = CARRY(D1_regM[0] & D1_reg[5]);


--J9_cs_buffer[1] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC5_B15
--operation mode is arithmetic

J9_cs_buffer[1] = D1_regM[0] $ D1_reg[5];

--J9_cout[1] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[1] at LC5_B15
--operation mode is arithmetic

J9_cout[1] = CARRY(D1_reg[5] # !D1_regM[0]);


--D1L93 is booth_mul:mul|reg~2868 at LC1_B15
--operation mode is normal

D1L93 = D1_reg[0] & !D1_reg[1] & J6_cs_buffer[0] # !D1_reg[0] & D1_reg[1] & J9_cs_buffer[1];


--D1L04 is booth_mul:mul|reg~2869 at LC3_B15
--operation mode is normal

D1L04 = D1L93 # D1_reg[5] & (D1_reg[0] $ !D1_reg[1]);


--D1L14 is booth_mul:mul|reg~2870 at LC4_B15
--operation mode is normal

D1L14 = D1L61 & D1L04 # !D1L61 & D1_reg[4];


--C1L93 is fast_div:div|reg~1131 at LC8_C5
--operation mode is normal

C1L93 = C1L02 & C1_reg[2] # !C1L02 & C1_reg[3];


--D1L24 is booth_mul:mul|reg~2872 at LC6_C18
--operation mode is normal

D1L24 = D1L61 & D1_reg[4] # !D1L61 & D1_reg[3];


--C1L04 is fast_div:div|reg~1133 at LC5_C6
--operation mode is normal

C1L04 = C1L02 & C1_reg[1] # !C1L02 & C1_reg[2];


--D1L34 is booth_mul:mul|reg~2874 at LC7_C18
--operation mode is normal

D1L34 = D1L61 & D1_reg[3] # !D1L61 & D1_reg[2];


--C1_reg[0] is fast_div:div|reg[0] at LC6_C6
--operation mode is normal

C1_reg[0]_lut_out = load & A[0] # !load & C1L24;
C1_reg[0] = DFFEA(C1_reg[0]_lut_out, GLOBAL(Clk), , , , , );


--C1L14 is fast_div:div|reg~1135 at LC7_C6
--operation mode is normal

C1L14 = C1L02 & C1_reg[0] # !C1L02 & C1_reg[1];


--D1_qout[0] is booth_mul:mul|qout[0] at LC6_C21
--operation mode is normal

D1_qout[0]_lut_out = D1_reg[1];
D1_qout[0] = DFFEA(D1_qout[0]_lut_out, GLOBAL(Clk), , , D1L8, , );


--C1_qout[0] is fast_div:div|qout[0] at LC1_C6
--operation mode is normal

C1_qout[0]_lut_out = C1_reg[0];
C1_qout[0] = DFFEA(C1_qout[0]_lut_out, GLOBAL(Clk), , , C1L21, , );


--A1L62 is Mux~819 at LC7_C21
--operation mode is normal

A1L62 = optional[0] & !C1_qout[0] # !optional[0] & !D1_qout[0] # !optional[1];


--A1L72 is Mux~821 at LC8_C21
--operation mode is normal

A1L72 = (optional[1] # A[0] $ Ci $ !B[0]) & CASCADE(A1L62);


--C1_regM[3] is fast_div:div|regM[3] at LC3_C2
--operation mode is normal

C1_regM[3]_lut_out = B[3];
C1_regM[3] = DFFEA(C1_regM[3]_lut_out, GLOBAL(Clk), , , load, , );


--G1_unreg_res_node[4] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[4] at LC4_C3
--operation mode is normal

G1_unreg_res_node[4] = C1_reg[6] $ J3_cout[3] $ C1_regM[3];


--C1L03 is fast_div:div|reg[7]~1137 at LC8_C8
--operation mode is normal

C1L03 = !load & (C1_Count[0] # C1_Count[1] # C1_Count[2]);


--D1L44 is booth_mul:mul|reg~2876 at LC8_C18
--operation mode is normal

D1L44 = D1L61 & D1_reg[2] # !D1L61 & D1_reg[1];


--D1_regM[3] is booth_mul:mul|regM[3] at LC2_B19
--operation mode is normal

D1_regM[3]_lut_out = A[3];
D1_regM[3] = DFFEA(D1_regM[3]_lut_out, GLOBAL(Clk), , , load, , );


--G2_unreg_res_node[3] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[3] at LC5_B16
--operation mode is normal

G2_unreg_res_node[3] = D1_regM[3] $ J6_cout[2] $ D1_reg[8];


--G3_unreg_res_node[4] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[4] at LC8_B15
--operation mode is normal

G3_unreg_res_node[4] = D1_reg[8] $ J9_cout[3] $ D1_regM[3];


--C1L24 is fast_div:div|reg~1138 at LC8_C6
--operation mode is normal

C1L24 = C1L02 & C1L9 # !C1L02 & C1_reg[0];


--C1_regM[2] is fast_div:div|regM[2] at LC1_C1
--operation mode is normal

C1_regM[2]_lut_out = B[2];
C1_regM[2] = DFFEA(C1_regM[2]_lut_out, GLOBAL(Clk), , , load, , );


--C1L7 is fast_div:div|LessThan~285 at LC6_C3
--operation mode is normal

C1L7 = C1_regM[3] & C1_reg[6] & (C1_reg[5] # !C1_regM[2]) # !C1_regM[3] & (C1_reg[5] # C1_reg[6] # !C1_regM[2]);


--C1L6 is fast_div:div|LessThan~15 at LC1_C2
--operation mode is normal

C1L6 = C1_regM[3] $ C1_reg[6];


--C1_regM[1] is fast_div:div|regM[1] at LC5_C5
--operation mode is normal

C1_regM[1]_lut_out = B[1];
C1_regM[1] = DFFEA(C1_regM[1]_lut_out, GLOBAL(Clk), , , load, , );


--C1_regM[0] is fast_div:div|regM[0] at LC4_C5
--operation mode is normal

C1_regM[0]_lut_out = B[0];
C1_regM[0] = DFFEA(C1_regM[0]_lut_out, GLOBAL(Clk), , , load, , );


--C1L8 is fast_div:div|LessThan~286 at LC1_C5
--operation mode is normal

C1L8 = C1_reg[4] & !C1_reg[3] & C1_regM[0] & C1_regM[1] # !C1_reg[4] & (C1_regM[1] # !C1_reg[3] & C1_regM[0]);


--C1L9 is fast_div:div|LessThan~288 at LC7_C3
--operation mode is normal

C1L9 = (C1L6 # C1_regM[2] $ C1_reg[5] # !C1L8) & CASCADE(C1L7);


--D1_regM[2] is booth_mul:mul|regM[2] at LC4_B18
--operation mode is normal

D1_regM[2]_lut_out = A[2];
D1_regM[2] = DFFEA(D1_regM[2]_lut_out, GLOBAL(Clk), , , load, , );


--D1_regM[1] is booth_mul:mul|regM[1] at LC1_B17
--operation mode is normal

D1_regM[1]_lut_out = A[1];
D1_regM[1] = DFFEA(D1_regM[1]_lut_out, GLOBAL(Clk), , , load, , );


--D1_regM[0] is booth_mul:mul|regM[0] at LC7_B16
--operation mode is normal

D1_regM[0]_lut_out = A[0];
D1_regM[0] = DFFEA(D1_regM[0]_lut_out, GLOBAL(Clk), , , load, , );


--optional[1] is optional[1] at PIN_2
--operation mode is input

optional[1] = INPUT();


--optional[0] is optional[0] at PIN_44
--operation mode is input

optional[0] = INPUT();


--Clk is Clk at PIN_43
--operation mode is input

Clk = INPUT();


--A[2] is A[2] at PIN_1
--operation mode is input

A[2] = INPUT();


--A[1] is A[1] at PIN_53
--operation mode is input

A[1] = INPUT();


--A[0] is A[0] at PIN_47
--operation mode is input

A[0] = INPUT();


--B[0] is B[0] at PIN_59
--operation mode is input

B[0] = INPUT();


--Ci is Ci at PIN_30
--operation mode is input

Ci = INPUT();


--B[1] is B[1] at PIN_36
--operation mode is input

B[1] = INPUT();


--B[2] is B[2] at PIN_28
--operation mode is input

B[2] = INPUT();


--A[3] is A[3] at PIN_42
--operation mode is input

A[3] = INPUT();


--B[3] is B[3] at PIN_83
--operation mode is input

B[3] = INPUT();


--load is load at PIN_84
--operation mode is input

load = INPUT();


--qout[7] is qout[7] at PIN_65
--operation mode is output

qout[7] = OUTPUT(A1L74Q);


--qout[6] is qout[6] at PIN_29
--operation mode is output

qout[6] = OUTPUT(A1L54Q);


--qout[5] is qout[5] at PIN_64
--operation mode is output

qout[5] = OUTPUT(A1L34Q);


--qout[4] is qout[4] at PIN_24
--operation mode is output

qout[4] = OUTPUT(A1L14Q);


--qout[3] is qout[3] at PIN_62
--operation mode is output

qout[3] = OUTPUT(A1L93Q);


--qout[2] is qout[2] at PIN_58
--operation mode is output

qout[2] = OUTPUT(A1L73Q);


--qout[1] is qout[1] at PIN_27
--operation mode is output

qout[1] = OUTPUT(A1L53Q);


--qout[0] is qout[0] at PIN_61
--operation mode is output

qout[0] = OUTPUT(A1L33Q);


--Co is Co at PIN_60
--operation mode is output

Co = OUTPUT(A1L41Q);


--done is done at PIN_66
--operation mode is output

done = OUTPUT(A1L61Q);