alu.map.eqn

实现4位加减乘除的alu

D1L33 = D1_reg[0] & G2_unreg_res_node[3] & !D1_reg[1] # !D1_reg[0] & !G3_unreg_res_node[4] & D1_reg[1];


--J3_cs_buffer[3] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

J3_cs_buffer[3] = C1_regM[2] $ C1_reg[5] $ J3_cout[2];

--J3_cout[3] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

J3_cout[3] = CARRY(C1_regM[2] & C1_reg[5] & J3_cout[2] # !C1_regM[2] & (C1_reg[5] # J3_cout[2]));


--C1L63 is fast_div:div|reg~1125
--operation mode is normal

C1L63 = C1_reg[5] & (!J3_cs_buffer[3] # !C1L9) # !C1_reg[5] & C1L9 & !J3_cs_buffer[3];


--D1L43 is booth_mul:mul|reg~2860
--operation mode is normal

D1L43 = D1L33 # D1_reg[8] & (D1_reg[1] $ !D1_reg[0]);


--J3_cs_buffer[2] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

J3_cs_buffer[2] = C1_regM[1] $ C1_reg[4] $ J3_cout[1];

--J3_cout[2] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

J3_cout[2] = CARRY(C1_regM[1] & C1_reg[4] & J3_cout[1] # !C1_regM[1] & (C1_reg[4] # J3_cout[1]));


--C1L73 is fast_div:div|reg~1127
--operation mode is normal

C1L73 = C1_reg[4] & (!J3_cs_buffer[2] # !C1L9) # !C1_reg[4] & C1L9 & !J3_cs_buffer[2];


--J6_cs_buffer[2] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

J6_cs_buffer[2] = D1_regM[2] $ D1_reg[7] $ J6_cout[1];

--J6_cout[2] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

J6_cout[2] = CARRY(D1_regM[2] & (D1_reg[7] # J6_cout[1]) # !D1_regM[2] & D1_reg[7] & J6_cout[1]);


--J9_cs_buffer[3] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

J9_cs_buffer[3] = D1_regM[2] $ D1_reg[7] $ J9_cout[2];

--J9_cout[3] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

J9_cout[3] = CARRY(D1_regM[2] & D1_reg[7] & J9_cout[2] # !D1_regM[2] & (D1_reg[7] # J9_cout[2]));


--D1L53 is booth_mul:mul|reg~2862
--operation mode is normal

D1L53 = D1_reg[0] & J6_cs_buffer[2] & !D1_reg[1] # !D1_reg[0] & !J9_cs_buffer[3] & D1_reg[1];


--D1L63 is booth_mul:mul|reg~2863
--operation mode is normal

D1L63 = D1L53 # D1_reg[7] & (D1_reg[1] $ !D1_reg[0]);


--J3_cs_buffer[1] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

J3_cs_buffer[1] = C1_reg[3] $ C1_regM[0];

--J3_cout[1] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

J3_cout[1] = CARRY(C1_reg[3] # !C1_regM[0]);


--C1L83 is fast_div:div|reg~1129
--operation mode is normal

C1L83 = J3_cs_buffer[1] & (C1_reg[3] # C1L9) # !J3_cs_buffer[1] & C1_reg[3] & !C1L9;


--J6_cs_buffer[1] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

J6_cs_buffer[1] = D1_regM[1] $ D1_reg[6] $ J6_cout[0];

--J6_cout[1] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

J6_cout[1] = CARRY(D1_regM[1] & (D1_reg[6] # J6_cout[0]) # !D1_regM[1] & D1_reg[6] & J6_cout[0]);


--J9_cs_buffer[2] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

J9_cs_buffer[2] = D1_regM[1] $ D1_reg[6] $ J9_cout[1];

--J9_cout[2] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

J9_cout[2] = CARRY(D1_regM[1] & D1_reg[6] & J9_cout[1] # !D1_regM[1] & (D1_reg[6] # J9_cout[1]));


--D1L73 is booth_mul:mul|reg~2865
--operation mode is normal

D1L73 = D1_reg[0] & J6_cs_buffer[1] & !D1_reg[1] # !D1_reg[0] & !J9_cs_buffer[2] & D1_reg[1];


--D1L83 is booth_mul:mul|reg~2866
--operation mode is normal

D1L83 = D1L73 # D1_reg[6] & (D1_reg[1] $ !D1_reg[0]);


--J6_cs_buffer[0] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

J6_cs_buffer[0] = D1_reg[5] $ D1_regM[0];

--J6_cout[0] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

J6_cout[0] = CARRY(D1_reg[5] & D1_regM[0]);


--J9_cs_buffer[1] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

J9_cs_buffer[1] = D1_reg[5] $ D1_regM[0];

--J9_cout[1] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

J9_cout[1] = CARRY(D1_reg[5] # !D1_regM[0]);


--D1L93 is booth_mul:mul|reg~2868
--operation mode is normal

D1L93 = D1_reg[1] & J9_cs_buffer[1] & !D1_reg[0] # !D1_reg[1] & J6_cs_buffer[0] & D1_reg[0];


--D1L04 is booth_mul:mul|reg~2869
--operation mode is normal

D1L04 = D1L93 # D1_reg[5] & (D1_reg[1] $ !D1_reg[0]);


--D1L14 is booth_mul:mul|reg~2870
--operation mode is normal

D1L14 = D1L04 & (D1_reg[4] # D1L61) # !D1L04 & D1_reg[4] & !D1L61;


--C1L93 is fast_div:div|reg~1131
--operation mode is normal

C1L93 = C1_reg[2] & (C1_reg[3] # C1L02) # !C1_reg[2] & C1_reg[3] & !C1L02;


--D1L24 is booth_mul:mul|reg~2872
--operation mode is normal

D1L24 = D1_reg[4] & (D1_reg[3] # D1L61) # !D1_reg[4] & D1_reg[3] & !D1L61;


--C1L04 is fast_div:div|reg~1133
--operation mode is normal

C1L04 = C1_reg[1] & (C1_reg[2] # C1L02) # !C1_reg[1] & C1_reg[2] & !C1L02;


--D1L34 is booth_mul:mul|reg~2874
--operation mode is normal

D1L34 = D1_reg[3] & (D1_reg[2] # D1L61) # !D1_reg[3] & D1_reg[2] & !D1L61;


--C1_reg[0] is fast_div:div|reg[0]
--operation mode is normal

C1_reg[0]_lut_out = A[0] & (C1L24 # load) # !A[0] & C1L24 & !load;
C1_reg[0] = DFFEA(C1_reg[0]_lut_out, Clk, , , , , );


--C1L14 is fast_div:div|reg~1135
--operation mode is normal

C1L14 = C1_reg[0] & (C1_reg[1] # C1L02) # !C1_reg[0] & C1_reg[1] & !C1L02;


--D1_qout[0] is booth_mul:mul|qout[0]
--operation mode is normal

D1_qout[0]_lut_out = D1_reg[1];
D1_qout[0] = DFFEA(D1_qout[0]_lut_out, Clk, , , D1L8, , );


--C1_qout[0] is fast_div:div|qout[0]
--operation mode is normal

C1_qout[0]_lut_out = C1_reg[0];
C1_qout[0] = DFFEA(C1_qout[0]_lut_out, Clk, , , C1L21, , );


--A1L62 is Mux~819
--operation mode is normal

A1L62 = optional[0] & !C1_qout[0] # !optional[0] & !D1_qout[0] # !optional[1];


--A1L72 is Mux~821
--operation mode is normal

A1L72 = (optional[1] # B[0] $ Ci $ !A[0]) & CASCADE(A1L62);


--C1_regM[3] is fast_div:div|regM[3]
--operation mode is normal

C1_regM[3]_lut_out = B[3];
C1_regM[3] = DFFEA(C1_regM[3]_lut_out, Clk, , , load, , );


--G1_unreg_res_node[4] is fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[4]
--operation mode is normal

G1_unreg_res_node[4] = C1_regM[3] $ C1_reg[6] $ J3_cout[3];


--C1L03 is fast_div:div|reg[7]~1137
--operation mode is normal

C1L03 = !load & (C1_Count[2] # C1_Count[1] # C1_Count[0]);


--D1L44 is booth_mul:mul|reg~2876
--operation mode is normal

D1L44 = D1_reg[2] & (D1_reg[1] # D1L61) # !D1_reg[2] & D1_reg[1] & !D1L61;


--D1_regM[3] is booth_mul:mul|regM[3]
--operation mode is normal

D1_regM[3]_lut_out = A[3];
D1_regM[3] = DFFEA(D1_regM[3]_lut_out, Clk, , , load, , );


--G2_unreg_res_node[3] is booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[3]
--operation mode is normal

G2_unreg_res_node[3] = D1_reg[8] $ D1_regM[3] $ J6_cout[2];


--G3_unreg_res_node[4] is booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[4]
--operation mode is normal

G3_unreg_res_node[4] = D1_regM[3] $ D1_reg[8] $ J9_cout[3];


--C1L24 is fast_div:div|reg~1138
--operation mode is normal

C1L24 = C1L9 & (C1_reg[0] # C1L02) # !C1L9 & C1_reg[0] & !C1L02;


--C1_regM[2] is fast_div:div|regM[2]
--operation mode is normal

C1_regM[2]_lut_out = B[2];
C1_regM[2] = DFFEA(C1_regM[2]_lut_out, Clk, , , load, , );


--C1L7 is fast_div:div|LessThan~285
--operation mode is normal

C1L7 = C1_reg[6] & (C1_reg[5] # !C1_regM[3] # !C1_regM[2]) # !C1_reg[6] & !C1_regM[3] & (C1_reg[5] # !C1_regM[2]);


--C1L6 is fast_div:div|LessThan~15
--operation mode is normal

C1L6 = C1_reg[6] $ C1_regM[3];


--C1_regM[1] is fast_div:div|regM[1]
--operation mode is normal

C1_regM[1]_lut_out = B[1];
C1_regM[1] = DFFEA(C1_regM[1]_lut_out, Clk, , , load, , );


--C1_regM[0] is fast_div:div|regM[0]
--operation mode is normal

C1_regM[0]_lut_out = B[0];
C1_regM[0] = DFFEA(C1_regM[0]_lut_out, Clk, , , load, , );


--C1L8 is fast_div:div|LessThan~286
--operation mode is normal

C1L8 = C1_regM[1] & (C1_regM[0] & !C1_reg[3] # !C1_reg[4]) # !C1_regM[1] & C1_regM[0] & !C1_reg[3] & !C1_reg[4];


--C1L9 is fast_div:div|LessThan~288
--operation mode is normal

C1L9 = (C1L6 # C1_reg[5] $ C1_regM[2] # !C1L8) & CASCADE(C1L7);


--D1_regM[2] is booth_mul:mul|regM[2]
--operation mode is normal

D1_regM[2]_lut_out = A[2];
D1_regM[2] = DFFEA(D1_regM[2]_lut_out, Clk, , , load, , );


--D1_regM[1] is booth_mul:mul|regM[1]
--operation mode is normal

D1_regM[1]_lut_out = A[1];
D1_regM[1] = DFFEA(D1_regM[1]_lut_out, Clk, , , load, , );


--D1_regM[0] is booth_mul:mul|regM[0]
--operation mode is normal

D1_regM[0]_lut_out = A[0];
D1_regM[0] = DFFEA(D1_regM[0]_lut_out, Clk, , , load, , );


--optional[1] is optional[1]
--operation mode is input

optional[1] = INPUT();


--optional[0] is optional[0]
--operation mode is input

optional[0] = INPUT();


--Clk is Clk
--operation mode is input

Clk = INPUT();


--A[2] is A[2]
--operation mode is input

A[2] = INPUT();


--A[1] is A[1]
--operation mode is input

A[1] = INPUT();


--A[0] is A[0]
--operation mode is input

A[0] = INPUT();


--B[0] is B[0]
--operation mode is input

B[0] = INPUT();


--Ci is Ci
--operation mode is input

Ci = INPUT();


--B[1] is B[1]
--operation mode is input

B[1] = INPUT();


--B[2] is B[2]
--operation mode is input

B[2] = INPUT();


--A[3] is A[3]
--operation mode is input

A[3] = INPUT();


--B[3] is B[3]
--operation mode is input

B[3] = INPUT();


--load is load
--operation mode is input

load = INPUT();


--qout[7] is qout[7]
--operation mode is output

qout[7] = OUTPUT(A1L74Q);


--qout[6] is qout[6]
--operation mode is output

qout[6] = OUTPUT(A1L54Q);


--qout[5] is qout[5]
--operation mode is output

qout[5] = OUTPUT(A1L34Q);


--qout[4] is qout[4]
--operation mode is output

qout[4] = OUTPUT(A1L14Q);


--qout[3] is qout[3]
--operation mode is output

qout[3] = OUTPUT(A1L93Q);


--qout[2] is qout[2]
--operation mode is output

qout[2] = OUTPUT(A1L73Q);


--qout[1] is qout[1]
--operation mode is output

qout[1] = OUTPUT(A1L53Q);


--qout[0] is qout[0]
--operation mode is output

qout[0] = OUTPUT(A1L33Q);


--Co is Co
--operation mode is output

Co = OUTPUT(A1L41Q);


--done is done
--operation mode is output

done = OUTPUT(A1L61Q);