alu.map.eqn

实现4位加减乘除的alu

--A1L74Q is qout[7]~reg0
--operation mode is normal

A1L74Q_lut_out = optional[1] & (optional[0] & C1_qout[7] # !optional[0] & D1_qout[7]);
A1L74Q = DFFEA(A1L74Q_lut_out, Clk, , , , , );


--A1L54Q is qout[6]~reg0
--operation mode is normal

A1L54Q_lut_out = optional[1] & (optional[0] & C1_qout[6] # !optional[0] & D1_qout[6]);
A1L54Q = DFFEA(A1L54Q_lut_out, Clk, , , , , );


--A1L34Q is qout[5]~reg0
--operation mode is normal

A1L34Q_lut_out = optional[1] & (optional[0] & C1_qout[5] # !optional[0] & D1_qout[5]);
A1L34Q = DFFEA(A1L34Q_lut_out, Clk, , , , , );


--A1L14Q is qout[4]~reg0
--operation mode is normal

A1L14Q_lut_out = optional[1] & (optional[0] & C1_qout[4] # !optional[0] & D1_qout[4]);
A1L14Q = DFFEA(A1L14Q_lut_out, Clk, , , , , );


--A1L93Q is qout[3]~reg0
--operation mode is normal

A1L93Q_lut_out = A1L81 & (C1_qout[3] # !optional[1]) # !A1L81 & D1_qout[3] & optional[1];
A1L93Q = DFFEA(A1L93Q_lut_out, Clk, , , , , );


--A1L73Q is qout[2]~reg0
--operation mode is normal

A1L73Q_lut_out = A1L91 & (C1_qout[2] # !optional[0]) # !A1L91 & !B2_Sum[2] & optional[0];
A1L73Q = DFFEA(A1L73Q_lut_out, Clk, , , , , );


--A1L53Q is qout[1]~reg0
--operation mode is normal

A1L53Q_lut_out = A1L02 & (C1_qout[1] # !optional[1]) # !A1L02 & D1_qout[1] & optional[1];
A1L53Q = DFFEA(A1L53Q_lut_out, Clk, , , , , );


--A1L33Q is qout[0]~reg0
--operation mode is normal

A1L33Q_lut_out = !A1L72;
A1L33Q = DFFEA(A1L33Q_lut_out, Clk, , , , , );


--A1L41Q is Co~reg0
--operation mode is normal

A1L41Q_lut_out = A1L42 # B1L3 & A1L52;
A1L41Q = DFFEA(A1L41Q_lut_out, Clk, , , , , );


--A1L61Q is done~reg0
--operation mode is normal

A1L61Q_lut_out = optional[0] & C1_done # !optional[0] & D1_done # !optional[1];
A1L61Q = DFFEA(A1L61Q_lut_out, Clk, , , , , );


--C1_qout[7] is fast_div:div|qout[7]
--operation mode is normal

C1_qout[7]_lut_out = C1_reg[7];
C1_qout[7] = DFFEA(C1_qout[7]_lut_out, Clk, , , C1L21, , );


--D1_qout[7] is booth_mul:mul|qout[7]
--operation mode is normal

D1_qout[7]_lut_out = D1_reg[8];
D1_qout[7] = DFFEA(D1_qout[7]_lut_out, Clk, , , D1L8, , );


--C1_qout[6] is fast_div:div|qout[6]
--operation mode is normal

C1_qout[6]_lut_out = C1_reg[6];
C1_qout[6] = DFFEA(C1_qout[6]_lut_out, Clk, , , C1L21, , );


--D1_qout[6] is booth_mul:mul|qout[6]
--operation mode is normal

D1_qout[6]_lut_out = D1_reg[7];
D1_qout[6] = DFFEA(D1_qout[6]_lut_out, Clk, , , D1L8, , );


--C1_qout[5] is fast_div:div|qout[5]
--operation mode is normal

C1_qout[5]_lut_out = C1_reg[5];
C1_qout[5] = DFFEA(C1_qout[5]_lut_out, Clk, , , C1L21, , );


--D1_qout[5] is booth_mul:mul|qout[5]
--operation mode is normal

D1_qout[5]_lut_out = D1_reg[6];
D1_qout[5] = DFFEA(D1_qout[5]_lut_out, Clk, , , D1L8, , );


--C1_qout[4] is fast_div:div|qout[4]
--operation mode is normal

C1_qout[4]_lut_out = C1_reg[4];
C1_qout[4] = DFFEA(C1_qout[4]_lut_out, Clk, , , C1L21, , );


--D1_qout[4] is booth_mul:mul|qout[4]
--operation mode is normal

D1_qout[4]_lut_out = D1_reg[5];
D1_qout[4] = DFFEA(D1_qout[4]_lut_out, Clk, , , D1L8, , );


--D1_qout[3] is booth_mul:mul|qout[3]
--operation mode is normal

D1_qout[3]_lut_out = D1_reg[4];
D1_qout[3] = DFFEA(D1_qout[3]_lut_out, Clk, , , D1L8, , );


--B2L1 is fast_sub:sub|fast_add:add|Carry~359
--operation mode is normal

B2L1 = A[0] & (!Ci # !B[0]) # !A[0] & !B[0] & !Ci;


--B2L2 is fast_sub:sub|fast_add:add|Carry~360
--operation mode is normal

B2L2 = A[1] & (B2L1 # !B[1]) # !A[1] & B2L1 & !B[1];


--B2L3 is fast_sub:sub|fast_add:add|Carry~361
--operation mode is normal

B2L3 = A[2] & (B2L2 # !B[2]) # !A[2] & B2L2 & !B[2];


--B2_Sum[3] is fast_sub:sub|fast_add:add|Sum[3]
--operation mode is normal

B2_Sum[3] = B2L3 $ A[3] $ B[3];


--B1L1 is fast_add:add|Carry~343
--operation mode is normal

B1L1 = B[0] & (Ci # A[0]) # !B[0] & Ci & A[0];


--B1L2 is fast_add:add|Carry~344
--operation mode is normal

B1L2 = A[1] & (B[1] # B1L1) # !A[1] & B[1] & B1L1;


--B1L3 is fast_add:add|Carry~345
--operation mode is normal

B1L3 = A[2] & (B[2] # B1L2) # !A[2] & B[2] & B1L2;


--B1_Sum[3] is fast_add:add|Sum[3]
--operation mode is normal

B1_Sum[3] = A[3] $ B[3] $ B1L3;


--A1L81 is Mux~36
--operation mode is normal

A1L81 = optional[0] & (optional[1] # !B2_Sum[3]) # !optional[0] & !optional[1] & B1_Sum[3];


--C1_qout[3] is fast_div:div|qout[3]
--operation mode is normal

C1_qout[3]_lut_out = C1_reg[3];
C1_qout[3] = DFFEA(C1_qout[3]_lut_out, Clk, , , C1L21, , );


--B2_Sum[2] is fast_sub:sub|fast_add:add|Sum[2]
--operation mode is normal

B2_Sum[2] = B2L2 $ A[2] $ B[2];


--D1_qout[2] is booth_mul:mul|qout[2]
--operation mode is normal

D1_qout[2]_lut_out = D1_reg[3];
D1_qout[2] = DFFEA(D1_qout[2]_lut_out, Clk, , , D1L8, , );


--B1_Sum[2] is fast_add:add|Sum[2]
--operation mode is normal

B1_Sum[2] = B1L2 $ A[2] $ B[2];


--A1L91 is Mux~38
--operation mode is normal

A1L91 = optional[1] & (optional[0] # D1_qout[2]) # !optional[1] & !optional[0] & B1_Sum[2];


--C1_qout[2] is fast_div:div|qout[2]
--operation mode is normal

C1_qout[2]_lut_out = C1_reg[2];
C1_qout[2] = DFFEA(C1_qout[2]_lut_out, Clk, , , C1L21, , );


--D1_qout[1] is booth_mul:mul|qout[1]
--operation mode is normal

D1_qout[1]_lut_out = D1_reg[2];
D1_qout[1] = DFFEA(D1_qout[1]_lut_out, Clk, , , D1L8, , );


--B2_Sum[1] is fast_sub:sub|fast_add:add|Sum[1]
--operation mode is normal

B2_Sum[1] = B2L1 $ A[1] $ B[1];


--B1_Sum[1] is fast_add:add|Sum[1]
--operation mode is normal

B1_Sum[1] = B1L1 $ A[1] $ B[1];


--A1L02 is Mux~40
--operation mode is normal

A1L02 = optional[0] & (optional[1] # !B2_Sum[1]) # !optional[0] & !optional[1] & B1_Sum[1];


--C1_qout[1] is fast_div:div|qout[1]
--operation mode is normal

C1_qout[1]_lut_out = C1_reg[1];
C1_qout[1] = DFFEA(C1_qout[1]_lut_out, Clk, , , C1L21, , );


--A1L12 is Mux~810
--operation mode is normal

A1L12 = optional[0] $ A[3];


--A1L22 is Mux~811
--operation mode is normal

A1L22 = optional[1] & A1L41Q # !optional[1] & A1L12 & B[3];


--A1L32 is Mux~812
--operation mode is normal

A1L32 = optional[0] & !optional[1] & (B[3] # !A[3]);


--A1L42 is Mux~813
--operation mode is normal

A1L42 = A1L22 # A1L32 & !B2L3;


--A1L52 is Mux~814
--operation mode is normal

A1L52 = !optional[0] & !optional[1] & (A[3] # B[3]);


--C1_done is fast_div:div|done
--operation mode is normal

C1_done_lut_out = !load & (C1_done # !C1L02);
C1_done = DFFEA(C1_done_lut_out, Clk, , , , , );


--D1_done is booth_mul:mul|done
--operation mode is normal

D1_done_lut_out = !load & (D1_done # !D1L61);
D1_done = DFFEA(D1_done_lut_out, Clk, , , , , );


--C1_reg[7] is fast_div:div|reg[7]
--operation mode is normal

C1_reg[7]_lut_out = C1_reg[6] & (!G1_unreg_res_node[4] # !C1L9) # !C1_reg[6] & C1L9 & !G1_unreg_res_node[4];
C1_reg[7] = DFFEA(C1_reg[7]_lut_out, Clk, , , C1L03, , );


--C1_Count[2] is fast_div:div|Count[2]
--operation mode is normal

C1_Count[2]_lut_out = load # C1_Count[2] & (C1_Count[1] # C1_Count[0]);
C1_Count[2] = DFFEA(C1_Count[2]_lut_out, Clk, , , , , );


--C1_Count[1] is fast_div:div|Count[1]
--operation mode is normal

C1_Count[1]_lut_out = C1L03 & (C1_Count[1] $ !C1_Count[0]);
C1_Count[1] = DFFEA(C1_Count[1]_lut_out, Clk, , , , , );


--C1_Count[0] is fast_div:div|Count[0]
--operation mode is normal

C1_Count[0]_lut_out = C1L03 & !C1_Count[0];
C1_Count[0] = DFFEA(C1_Count[0]_lut_out, Clk, , , , , );


--C1L21 is fast_div:div|qout[0]~15
--operation mode is normal

C1L21 = !load & !C1_Count[2] & !C1_Count[1] & !C1_Count[0];


--D1_reg[8] is booth_mul:mul|reg[8]
--operation mode is normal

D1_reg[8]_lut_out = !load & (D1L23 # D1L61 & D1L33);
D1_reg[8] = DFFEA(D1_reg[8]_lut_out, Clk, , , , , );


--D1_Count[2] is booth_mul:mul|Count[2]
--operation mode is normal

D1_Count[2]_lut_out = load # D1_Count[2] & (D1_Count[1] # D1_Count[0]);
D1_Count[2] = DFFEA(D1_Count[2]_lut_out, Clk, , , , , );


--D1_Count[1] is booth_mul:mul|Count[1]
--operation mode is normal

D1_Count[1]_lut_out = !load & (D1_Count[1] & D1_Count[0] # !D1_Count[1] & !D1_Count[0] & D1_Count[2]);
D1_Count[1] = DFFEA(D1_Count[1]_lut_out, Clk, , , , , );


--D1_Count[0] is booth_mul:mul|Count[0]
--operation mode is normal

D1_Count[0]_lut_out = !D1_Count[0] & !load & (D1_Count[2] # D1_Count[1]);
D1_Count[0] = DFFEA(D1_Count[0]_lut_out, Clk, , , , , );


--D1L8 is booth_mul:mul|qout[0]~15
--operation mode is normal

D1L8 = !load & !D1_Count[2] & !D1_Count[1] & !D1_Count[0];


--C1_reg[6] is fast_div:div|reg[6]
--operation mode is normal

C1_reg[6]_lut_out = !load & (C1L02 & C1L63 # !C1L02 & C1_reg[6]);
C1_reg[6] = DFFEA(C1_reg[6]_lut_out, Clk, , , , , );


--D1_reg[7] is booth_mul:mul|reg[7]
--operation mode is normal

D1_reg[7]_lut_out = !load & (D1L61 & D1L43 # !D1L61 & D1_reg[7]);
D1_reg[7] = DFFEA(D1_reg[7]_lut_out, Clk, , , , , );


--C1_reg[5] is fast_div:div|reg[5]
--operation mode is normal

C1_reg[5]_lut_out = !load & (C1L02 & C1L73 # !C1L02 & C1_reg[5]);
C1_reg[5] = DFFEA(C1_reg[5]_lut_out, Clk, , , , , );


--D1_reg[6] is booth_mul:mul|reg[6]
--operation mode is normal

D1_reg[6]_lut_out = !load & (D1L61 & D1L63 # !D1L61 & D1_reg[6]);
D1_reg[6] = DFFEA(D1_reg[6]_lut_out, Clk, , , , , );


--C1_reg[4] is fast_div:div|reg[4]
--operation mode is normal

C1_reg[4]_lut_out = !load & (C1L02 & C1L83 # !C1L02 & C1_reg[4]);
C1_reg[4] = DFFEA(C1_reg[4]_lut_out, Clk, , , , , );


--D1_reg[5] is booth_mul:mul|reg[5]
--operation mode is normal

D1_reg[5]_lut_out = !load & (D1L61 & D1L83 # !D1L61 & D1_reg[5]);
D1_reg[5] = DFFEA(D1_reg[5]_lut_out, Clk, , , , , );


--D1_reg[4] is booth_mul:mul|reg[4]
--operation mode is normal

D1_reg[4]_lut_out = B[3] & (D1L14 # load) # !B[3] & D1L14 & !load;
D1_reg[4] = DFFEA(D1_reg[4]_lut_out, Clk, , , , , );


--C1_reg[3] is fast_div:div|reg[3]
--operation mode is normal

C1_reg[3]_lut_out = A[3] & (C1L93 # load) # !A[3] & C1L93 & !load;
C1_reg[3] = DFFEA(C1_reg[3]_lut_out, Clk, , , , , );


--D1_reg[3] is booth_mul:mul|reg[3]
--operation mode is normal

D1_reg[3]_lut_out = B[2] & (D1L24 # load) # !B[2] & D1L24 & !load;
D1_reg[3] = DFFEA(D1_reg[3]_lut_out, Clk, , , , , );


--C1_reg[2] is fast_div:div|reg[2]
--operation mode is normal

C1_reg[2]_lut_out = A[2] & (C1L04 # load) # !A[2] & C1L04 & !load;
C1_reg[2] = DFFEA(C1_reg[2]_lut_out, Clk, , , , , );


--D1_reg[2] is booth_mul:mul|reg[2]
--operation mode is normal

D1_reg[2]_lut_out = B[1] & (D1L34 # load) # !B[1] & D1L34 & !load;
D1_reg[2] = DFFEA(D1_reg[2]_lut_out, Clk, , , , , );


--C1_reg[1] is fast_div:div|reg[1]
--operation mode is normal

C1_reg[1]_lut_out = A[1] & (C1L14 # load) # !A[1] & C1L14 & !load;
C1_reg[1] = DFFEA(C1_reg[1]_lut_out, Clk, , , , , );


--C1L02 is fast_div:div|reduce_or~0
--operation mode is normal

C1L02 = C1_Count[2] # C1_Count[1] # C1_Count[0];


--D1L61 is booth_mul:mul|reduce_or~0
--operation mode is normal

D1L61 = D1_Count[2] # D1_Count[1] # D1_Count[0];


--D1_reg[1] is booth_mul:mul|reg[1]
--operation mode is normal

D1_reg[1]_lut_out = B[0] & (D1L44 # load) # !B[0] & D1L44 & !load;
D1_reg[1] = DFFEA(D1_reg[1]_lut_out, Clk, , , , , );


--D1_reg[0] is booth_mul:mul|reg[0]
--operation mode is normal

D1_reg[0]_lut_out = !load & (D1L61 & D1_reg[1] # !D1L61 & D1_reg[0]);
D1_reg[0] = DFFEA(D1_reg[0]_lut_out, Clk, , , , , );


--D1L23 is booth_mul:mul|reg~2857
--operation mode is normal

D1L23 = D1_reg[8] & (D1_reg[1] $ !D1_reg[0] # !D1L61);


--D1L33 is booth_mul:mul|reg~2858
--operation mode is normal