📄 smbus_control.vhd
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-- smbus_control.vhd
--
-- Created: 6/14/00 JRH
-- This code implements the control of the smbus bus
-- created from i2c code developed by ALS 6/99.
--
-- Revised: 6/15/00 JRH
-- Modified constants to reflect using a 66MHz system clock. This is divided to
-- give an SCL clock frequency of 66kHz. The constants were also changed to meet
-- the SMBus timing requirements.
-- Revised: 6/20/00 JRH
-- Modified the SCL state machine and the Main state machine to make the repeated
-- start work. Fixed hold time for repeated start. Added Tbuf which is bus free
-- time between STOP and START condition.
-- Revised: 6/22/00 ALS
-- Changed name of constant BUS_FREE to TBUF since that is the parameter in the
-- I2C specification. The name BUS_FREE may be needed if it becomes necessary to
-- set a status bit when the I2C bus is free.
-- Revised: 6/28/00 JRH
-- Changed the 9 bit counter to 21 bits. Added count for scl low timeout.
-- Revised: 7/7/00 JRH
-- Changed the 21 bit scl counter back to 9 bits. Added a 21 bit counter for
-- the SCL low timeout and SCL/SDA high timeout
-- Revised: 7/10/00 JRH
-- Changed DATA_HOLD to be 1000ns to lengthen the data hold requirement. Spec is
-- 300ns min.
-- Revised: 9/1/00 JRH
-- Modified bus high timeout case where the controller resets only when bus high timeout
-- condition exists during a data transfer. This was to fix the issue where the
-- controller would reset during idle states and SDA/SCL were high for long periods
-- of time due to the weak pullup on the bus.
-- Revised: 8/6/00 JRH
-- Modified the main state machine to allow for the 8 bit shift register to re-load the
-- data on repeated starts. This was implemented by forcing the next state to be HEADER
-- during XMIT_DATA and RCV_DATA states. The 4 bit up counter was modified to reset
-- during a detect_start condition to count the correct number of bits during a repeated
-- start.
-- Revised: 2/15/02 JRH
-- Modified the arb_lost equations to test for sda_in different than sda one cyle
-- earlier due to timing issues.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity smbus_control is
port(
-- SMBUS bus signals
sda : inout std_logic;
scl : inout std_logic;
-- interface signals from uP interface
txak : in std_logic; -- value for acknowledge when xmit
msta : in std_logic; -- master/slave select
msta_rst : out std_logic; -- resets MSTA bit if arbitration is lost
rsta : in std_logic; -- repeated start
rsta_rst : out std_logic; -- modify rsta register
mtx : in std_logic; -- master read/write
mbdr_micro : in std_logic_vector(7 downto 0); -- uP data to output on SMBUS bus
madr : in std_logic_vector(7 downto 0); -- SMBUS slave address
mbb : out std_logic; -- bus busy
mcf : inout std_logic; -- data transfer
maas : inout std_logic; -- addressed as slave
mal : inout std_logic; -- arbitration lost
srw : inout std_logic; -- slave read/write
mif : out std_logic; -- interrupt pending
rxak : out std_logic; -- received acknowledge
mbdr_smbus : inout std_logic_vector(7 downto 0); -- SMBUS data for uP
mbcr_wr : in std_logic; -- indicates that MCBR register was written
mif_bit_reset : in std_logic; -- indicates that the MIF bit should be reset
mal_bit_reset : in std_logic; -- indicates that the MAL bit should be reset
men_bit_reset : out std_logic; -- indicates that the MEN bit should be reset
sys_clk : in std_logic;
reset : in std_logic);
end smbus_control;
library IEEE;
use IEEE.std_logic_1164.all;
architecture behave of smbus_control is
constant CNT_100KHZ : std_logic_vector(9 downto 0) := "1111101000"; -- number of 66MHz clocks in 66KHz
constant HIGH_CNT : std_logic_vector(8 downto 0) := "111110010"; -- number of 66MHz clocks in half
-- 66KHz period -1 since count from 0
-- and -1 for "edge" state
constant LOW_CNT : std_logic_vector(8 downto 0) := "111110010"; -- number of 66Mhz clocks in half
-- 66KHZ period -1 since count from 0
-- and -1 for "edge" state
constant STOP_REP_START_SU : std_logic_vector(8 downto 0) := "100111010"; -- stop and repeated start condition
-- setup time of 4.7us
constant TBUF : std_logic_vector(8 downto 0) := "100111010"; -- Bus free time between stop and start condition
constant DATA_HOLD : std_logic_vector(8 downto 0) := "001000010"; -- number of 66MHz clocks in 1us to meet 300ns min hold time
constant BUS_HIGH_TIMEOUT : std_logic_vector(20 downto 0) := "000000000110100000110"; -- number of 66MHz clocks in 50us
constant BUS_LOW_TIMEOUT : std_logic_vector(20 downto 0) := "110010110111001101010"; -- number of 66MHz clocks in 25ms
constant START_HOLD : std_logic_vector(8 downto 0) := "100001011"; --number of 66MHz clocks in 4.0us
constant CLR_REG : std_logic_vector(7 downto 0) := "00000000";
constant START_CNT : std_logic_vector(3 downto 0) := "0000";
constant CNT_DONE : std_logic_vector(3 downto 0) := "0111";
constant ZERO_CNT : std_logic_vector(8 downto 0) := "000000000";
constant TIMEOUT_ZERO_CNT : std_logic_vector(20 downto 0) := "000000000000000000000";
constant ZERO : std_logic := '0';
constant RESET_ACTIVE : std_logic := '0';
-- 8-bit serial load/parallel shift register
component SHIFT8
port(
clk : in std_logic; -- Clock
clr : in std_logic; -- Active low clear
data_ld : in std_logic; -- Data load enable
data_in : in std_logic_vector (7 downto 0); -- 8-bit data to load
shift_in : in std_logic; -- Serial data in
shift_en : in std_logic; -- Shift enable
shift_out : out std_logic; -- Bit to shift out
data_out : out std_logic_vector (7 downto 0)); -- 8-bit parallel out
end component;
-- Up counter - 21 bit
component UPCNT21
port(
data : in std_logic_vector (20 downto 0); -- Serial data in
cnt_en : in std_logic; -- Count enable
load : in std_logic; -- Load line enable
clr : in std_logic; -- Active low clear
clk : in std_logic; -- Clock
qout : inout std_logic_vector (20 downto 0));
end component;
-- Up counter - 9 bit
component UPCNT9
port(
data : in std_logic_vector (8 downto 0); -- Serial data in
cnt_en : in std_logic; -- Count enable
load : in std_logic; -- Load line enable
clr : in std_logic; -- Active low clear
clk : in std_logic; -- Clock
qout : inout std_logic_vector (8 downto 0));
end component;
-- Up counter - 4 bit
component UPCNT4
port(
data : in std_logic_vector (3 downto 0); -- Serial data in
cnt_en : in std_logic; -- Count enable
load : in std_logic; -- Load line enable
clr : in std_logic; -- Active low clear
clk : in std_logic; -- Clock
qout : inout std_logic_vector (3 downto 0));
end component;
type state_type is (IDLE, HEADER, ACK_HEADER, RCV_DATA, ACK_DATA,
XMIT_DATA, WAIT_ACK);
signal state : state_type;
type scl_state_type is (SCL_IDLE, START, SCL_LOW_EDGE, SCL_LOW, SCL_HIGH_EDGE,
SCL_HIGH, STOP_WAIT);
signal scl_state, next_scl_state : scl_state_type;
type watchdog_type is (WATCHDOG_IDLE, HIGH_COUNT, LOW_COUNT, WATCHDOG_RESET);
signal watchdog_state, next_watchdog_state : watchdog_type;
signal scl_in : std_logic; -- sampled version of scl
signal scl_out : std_logic; -- combinatorial scl output from scl generator state machine
signal scl_out_reg : std_logic; -- registered version of SCL_OUT
signal scl_not : std_logic; -- inverted version of SCL
signal sda_in : std_logic; -- sampled version of sda
signal sda_out : std_logic; -- combinatorial sda output from scl generator state machine
signal sda_out_reg : std_logic; -- registered version of SDA_OUT
signal sda_out_reg_d1 : std_logic; -- delayed sda output
--signal sda_out_reg_d2 : std_logic; -- sda output delayed one more clock for arbitration comparison
signal slave_sda : std_logic; -- sda value when slave
signal master_sda : std_logic; -- sda value when master
signal sda_oe : std_logic;
signal master_slave : std_logic; -- 1 if master, 0 if slave
-- Shift Register and the controls
signal shift_reg : std_logic_vector(7 downto 0); -- shift register that holds SMBUS data
signal shift_out : std_logic;
signal shift_reg_en, shift_reg_ld : std_logic;
signal smbus_header : std_logic_vector(7 downto 0); -- shift register that holds SMBUS header
signal smbus_header_en, smbus_header_ld : std_logic;
signal smbus_shiftout : std_logic;
-- Used to check slave address detected
signal addr_match : std_logic;
signal arb_lost : std_logic; -- 1 if arbitration is lost
signal msta_d1 : std_logic; -- delayed sample of msta
signal detect_start : std_logic; -- indicates that a START condition has been detected
signal detect_stop : std_logic; -- indicates that a STOP condition has been detected
signal sm_stop : std_logic; -- indicates that a STOP condition needs to be generated
-- from state machine
signal bus_busy : std_logic; -- indicates that the bus is busy - set when START, cleared when STOP
signal bus_busy_d1 : std_logic; -- delayed sample of bus busy used to determine MAL
signal gen_start : std_logic; -- indicates that the uP wants to generate a START
signal gen_stop : std_logic; -- indicates that the uP wants to generate a STOP
signal rep_start : std_logic; -- indicates that the uP wants to generate a repeated START
signal rep_start_det : std_logic; -- indicates that the rep_start is pending
signal rep_start_det_reg: std_logic; -- registered version of rep_start_det
signal stop_scl : std_logic; -- signal in SCL state machine indicating a STOP
signal stop_scl_reg : std_logic; -- registered version of STOP_SCL
-- Bit counter 0 to 7
signal bit_cnt : std_logic_vector(3 downto 0);
signal bit_cnt_ld, bit_cnt_clr, bit_cnt_en : std_logic;
-- Clock Counter
signal clk_cnt : std_logic_vector (8 downto 0);
signal clk_cnt_rst : std_logic;
signal clk_cnt_en : std_logic;
-- Watchdog Counter
signal timeout_cnt : std_logic_vector (20 downto 0);
signal timeout_cnt_rst : std_logic;
signal timeout_cnt_en : std_logic;
-- the following signals are only here because Viewlogic's VHDL compiler won't allow a constant
-- to be used in a component instantiation
signal reg_clr : std_logic_vector(7 downto 0);
signal zero_sig : std_logic;
signal cnt_zero : std_logic_vector(8 downto 0);
signal timeout_cnt_zero : std_logic_vector(20 downto 0);
signal cnt_start : std_logic_vector(3 downto 0);
begin
-- set SDA and SCL
sda <= '0' when sda_oe = '1' else 'Z';
scl <= '0' when scl_out_reg = '0' else 'Z';
scl_not <= not(scl);
-- sda_oe is set when master and arbitration is not lost and data to be output = 0 or
-- when slave and data to be output is 0
sda_oe <= '1' when ((master_slave = '1' and arb_lost = '0' and sda_out_reg = '0') or
(master_slave = '0' and slave_sda = '0')
or stop_scl_reg = '1') else '0';
-- the following signals are only here because Viewlogic's VHDL compiler won't allow a constant
-- to be used in a component instantiation
reg_clr <= CLR_REG;
zero_sig <= ZERO;
cnt_zero <= ZERO_CNT;
timeout_cnt_zero <= TIMEOUT_ZERO_CNT;
cnt_start <= START_CNT;
-- ************************ Arbitration Process ************************
-- This process checks the master's outgoing SDA with the incoming SDA to determine
-- if control of the bus has been lost. SDA is checked only when SCL is high
-- and during the states IDLE, HEADER, and XMIT_DATA to insure that START and STOP
-- conditions are not set when the bus is busy. Note that this is only done when Master.
-- When arbitration is lost, a reset is generated for the MSTA bit
-- Note that when arbitration is lost, the mode is switched to slave and SCL continues
-- to be generated until the byte transfer is complete
-- arb_lost stays set until scl state machine goes to IDLE state
arbitration: process (sys_clk, reset)
begin
if reset = RESET_ACTIVE then
arb_lost <= '0';
msta_rst <= '0';
elsif (sys_clk'event and sys_clk = '1') then
if scl_state = SCL_IDLE then
arb_lost <= '0';
msta_rst <= '0';
elsif (master_slave = '1') then
-- only need to check arbitration in master mode
-- check for SCL high before comparing data and insure that arb_lost is
-- not already set
if (scl_in = '1' and scl = '1' and arb_lost = '0'
and (state = HEADER or state = XMIT_DATA or state = IDLE)) then
-- when master, will check bus in all states except ACK_HEADER and WAIT_ACK
-- this will insure that arb_lost is set if a start or stop condition
-- is set at the wrong time
if sda_out_reg_d1 = sda_in then
arb_lost <= '0';
msta_rst <= '0';
else
arb_lost <= '1';
msta_rst <= '1';
end if;
else
arb_lost <= arb_lost;
msta_rst <= '0';
end if;
end if;
end if;
end process;
-- ************************ scl_watchdog Process ************************
-- This process monitors the SCL and SDA bus values to determine when two timing
-- conditions have been violated:
-- 1) T_timeout of 25 ms min for SMBus is when SCL has been low for 25 ms as
-- specified by the BUS_LOW_TIMEOUT constant. When this time has been reached,
-- the MEN bit of the uC Control Register is cleared which resets the SMBus
-- master or slave.
-- 2) T_high of 50 us max for SMBus is when SCL and SDA are both high for 50 us
-- max as specified by the BUS_HIGH_TIMEOUT constant. When this condition
-- occurs, the SMBus is considered free and the MBB bit (Bus Busy Bit) of
-- the uC Status Register is cleared indicating the bus is no longer busy.
scl_watchdog_comb: process (scl_in, sda_in, timeout_cnt, watchdog_state, bus_busy)
begin
-- state machine defaults
next_watchdog_state <= watchdog_state;
men_bit_reset <= not (RESET_ACTIVE);
timeout_cnt_rst <= '1';
timeout_cnt_en <= '0';
case watchdog_state is
when WATCHDOG_IDLE =>
if scl_in = '0' then
timeout_cnt_rst <= '0';
timeout_cnt_en <= '1';
next_watchdog_state <= LOW_COUNT;
else
if sda_in = '1' then
timeout_cnt_rst <= '0';
timeout_cnt_en <= '1';
next_watchdog_state <= HIGH_COUNT;
end if;
end if;
when HIGH_COUNT =>
timeout_cnt_rst <= '0';
timeout_cnt_en <= '1';
if scl_in = '0' then
timeout_cnt_rst <= '1';
next_watchdog_state <= LOW_COUNT;
end if;
if scl_in = '1' and sda_in = '0' then
next_watchdog_state <= WATCHDOG_IDLE;
end if;
if timeout_cnt = BUS_HIGH_TIMEOUT and bus_busy = '1' then
next_watchdog_state <= WATCHDOG_RESET;
end if;
when LOW_COUNT =>
timeout_cnt_rst <= '0';
timeout_cnt_en <= '1';
if scl_in = '1' then
timeout_cnt_rst <= '1';
next_watchdog_state <= HIGH_COUNT;
end if;
if timeout_cnt = BUS_LOW_TIMEOUT then
next_watchdog_state <= WATCHDOG_RESET;
end if;
when WATCHDOG_RESET =>
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