micro_tb.vhd
来自「可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序」· VHDL 代码 · 共 729 行 · 第 1/2 页
VHD
729 行
-- micro_tb.vhd
--
-- Created: 6/15/00 JRH
-- Created from a copy of the I2C micro_tb created by ALS.
-- This file emulates the uC that interfaces to the SMBUS design. This testbench
-- will interface to two instantiations of the SMBUS design, one will be configured as
-- a master, the other as a slave.
-- Revised: 6/15/00 JRH
-- Changed system clock frequency to 66MHz.
-- Revised: 6/15/00 JRH
-- Added a test for repeated start.
-- Revised: 6/26/00 ALS
-- Changed micro-controller state machine to model Hitachi SH7750.
-- Revised: 7/12/00 JRH
-- Modified to test a master only SMBus device together with a master/slave SMBus device.
-- Revised: 8/11/00 ALS
-- Changed micro-controller state machine to handle variable wait states and setup/hold states.
--
-- Modified: 8-14-00 JRH
-- Changed addresses for MBCR, MBSR, MBDR to even numbers.
-- Modified 11-27-00 JRH
-- Changed back to two master/slave SMBus devices: One configured as a master, the other
-- configured as a slave.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity micro_tb is
port (
-- inputs
irq : in std_logic;
mcf : in std_logic; -- indicates that SMBUS data transfer is complete
-- outputs
master_cs_n : out std_logic; -- active low chip select for master
slave_cs_n : out std_logic; -- active low chip select for slave
bs_n : out std_logic; -- active low bus select
we_n : out std_logic; -- active low write enable
rd_n : out std_logic; -- active low read enable
rd_wrn : out std_logic; -- active high read, active low write
-- ready signals
master_rdyn : in std_logic; -- active low ready signal from master
slave_rdyn : in std_logic; -- active low ready signal from slave
address : out std_logic_vector(7 downto 0);
reset : inout std_logic;
clk : inout std_logic;
data_match : out std_logic;
-- bi-direct
data_bus : inout std_logic_vector(7 downto 0)
);
end micro_tb;
architecture RTL of micro_tb is
-- ************************************* Constant Declarations **************************
constant RESET_ACTIVE : STD_LOGIC := '0';
constant CLK_PERIOD : time := 15 nS;
-- register addresses
constant MASTR_MBASE : STD_LOGIC_VECTOR(15 downto 0) := "0000000000001111"; -- Base Address (addr_bus[23:8])
constant SLAVE_MBASE : STD_LOGIC_VECTOR(15 downto 0) := "0000000000001101"; -- Base Address (addr_bus[23:8])
constant MADR_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "10001100"; -- Address Register (MBASE + 8Ch)
-- constant MFDR_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "10001111"; -- Frequency Divider Register (MBASE + 143h)
constant MBCR_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "10010000"; -- Control Register (MBASE + 90h)
constant MBSR_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "10010010"; -- Status Register (MBASE + 92h)
constant MBDR_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "10010100"; -- Data I/O Register (MBASE + 94h)
-- data words
constant ALL_ONES : std_logic_vector(7 downto 0) := "11111111";
constant ALL_ZEROS : std_logic_vector(7 downto 0) := "00000000";
constant MASTR_ADDR : std_logic_vector(7 downto 0) := "11110000";
constant SLAVE_ADDR : std_logic_vector(7 downto 0) := "00001110";
--constant SLAVE_ADDR : std_logic_vector(7 downto 0) := "10001110";
constant MASTR_MBCR_TX : std_logic_vector(7 downto 0) := "11010000";
constant MASTR_MBCR_RX : std_logic_vector(7 downto 0) := "11000000";
constant MASTR_MBCR_RX_REPEAT : std_logic_vector(7 downto 0) := "11100000";
constant SLAVE_MBCR : std_logic_vector(7 downto 0) := "11000000";
constant START_TX : std_logic_vector(7 downto 0) := "11110000";
constant START_RX : std_logic_vector(7 downto 0) := "11100000";
constant REPEAT_START_RX : std_logic_vector(7 downto 0) := "11100100";
constant NO_ACK : std_logic_vector(7 downto 0) := "11101000";
constant STOP_TX : std_logic_vector(7 downto 0) := "11010000";
constant STOP_RX : std_logic_vector(7 downto 0) := "11001000";
constant MFDR : std_logic_vector(7 downto 0) := "00000001";
constant TST_ADDR_OUT_HEADER : std_logic_vector(7 downto 0) := "00001110";
constant MASTR_RD_HEADER : std_logic_vector(7 downto 0) := "00001111";
--constant TST_ADDR_OUT_HEADER : std_logic_vector(7 downto 0) := "10001110";
--constant MASTR_RD_HEADER : std_logic_vector(7 downto 0) := "10001111";
constant DE : std_logic_vector(7 downto 0) := "11011110";
constant AD : std_logic_vector(7 downto 0) := "10101101";
constant BE : std_logic_vector(7 downto 0) := "10111110";
constant EF : std_logic_vector(7 downto 0) := "11101111";
constant FA : std_logic_vector(7 downto 0) := "11111010";
constant CE : std_logic_vector(7 downto 0) := "11001110";
-- constants to control number of wait states and setup/hold states
constant WAIT_STATES : unsigned(3 downto 0) := "0001"; -- total internal + external wait states
constant SETUP_STATES : unsigned(3 downto 0) := "0001"; -- desired setup states
constant HOLD_STATES : unsigned(3 downto 0) := "0001"; -- desired hold states
-- number of words in the data packet
constant LAST_WORD : integer := 4;
constant LOGIC_DELAY : time := 4 nS;
-- test data
type TEST_DATA is array (0 to 44) of std_logic_vector (7 downto 0);
constant TST_DATA_OUT : TEST_DATA := (
(MASTR_ADDR), -- write master's SMBUS address
(SLAVE_ADDR), -- write slave's SMBUS address
(MASTR_MBCR_TX), -- enable the master to transmit
(SLAVE_MBCR), -- enable the slave
(TST_ADDR_OUT_HEADER), -- write the header
(START_TX), -- generate START
(DE), -- write the data to the Master
(AD),
(BE),
(EF),
(FA),
(DE),
(STOP_TX),
(ALL_ONES),
(ALL_ONES),
(ALL_ONES), -- dummy for status register read
(MASTR_MBCR_RX), -- enable the master to receive
(MASTR_RD_HEADER), -- write the header with slave to transmit
(START_RX), -- generate START
(DE), -- write the data to the slave
(AD),
(BE),
(EF),
(FA),
(DE),
(NO_ACK), -- turn off Master's acknowledge to end cycle
(STOP_RX), -- generate STOP
--beginning of repeat start test
(ALL_ONES),
(ALL_ONES),
(ALL_ONES), -- dummy for status register read
(MASTR_MBCR_TX), -- enable the master to transmit
(TST_ADDR_OUT_HEADER), -- write the header
(START_TX), -- generate START
(BE), -- write the data to the Master
(MASTR_MBCR_RX_REPEAT), -- enable the master to receive
(MASTR_RD_HEADER), -- write the header with slave to transmit
(REPEAT_START_RX), -- generate repeated START
(AD), -- write the data to the slave
(BE),
(EF),
(FA),
(DE),
(AD),
(NO_ACK), -- turn off Master's acknowledge to end cycle
(STOP_RX) -- generate STOP
);
type TEST_ADDR is array (0 to 44) of std_logic_vector( 23 downto 0);
constant TST_ADDR_OUT : TEST_ADDR := (
(MASTR_MBASE & MADR_ADDR), -- write master's SMBUS address
(SLAVE_MBASE & MADR_ADDR), -- write slave's SMBUS address
(MASTR_MBASE & MBCR_ADDR), -- enable the master to transmit
(SLAVE_MBASE & MBCR_ADDR), -- enable the slave
(MASTR_MBASE & MBDR_ADDR), -- write the smbus header
(MASTR_MBASE & MBCR_ADDR), -- generate start
(MASTR_MBASE & MBDR_ADDR), -- write the data
(MASTR_MBASE & MBDR_ADDR), -- write the data
(MASTR_MBASE & MBDR_ADDR), -- write the data
(MASTR_MBASE & MBDR_ADDR), -- write the data
(MASTR_MBASE & MBDR_ADDR), -- write the data
(MASTR_MBASE & MBDR_ADDR), -- write the data
(MASTR_MBASE & MBCR_ADDR), -- generate stop
(MASTR_MBASE & MBSR_ADDR), -- read Master's status register
(SLAVE_MBASE & MBSR_ADDR), -- read Slave's status register
(MASTR_MBASE & MADR_ADDR), -- read Master's address register
(MASTR_MBASE & MBCR_ADDR), -- enable Master to receive
(MASTR_MBASE & MBDR_ADDR), -- write the header for slave to transmit
(MASTR_MBASE & MBCR_ADDR), -- generate START
(SLAVE_MBASE & MBDR_ADDR), -- write data to the slave
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR), -- write last data word
(MASTR_MBASE & MBCR_ADDR), -- turn off Master's ACK
(MASTR_MBASE & MBCR_ADDR), -- generate STOP
--beginning of repeat start test
(MASTR_MBASE & MBSR_ADDR), -- read Master's status register
(SLAVE_MBASE & MBSR_ADDR), -- read Slave's status register
(MASTR_MBASE & MADR_ADDR), -- read Master's address register
(MASTR_MBASE & MBCR_ADDR), -- enable Master to transmit
(MASTR_MBASE & MBDR_ADDR), -- write the header with slave's address
(MASTR_MBASE & MBCR_ADDR), -- generate START
(MASTR_MBASE & MBDR_ADDR), -- write data to the master
(MASTR_MBASE & MBCR_ADDR), -- enable Master to receive
(MASTR_MBASE & MBDR_ADDR), -- write the header with slave's address
(MASTR_MBASE & MBCR_ADDR), -- generate repeated START
(SLAVE_MBASE & MBDR_ADDR), -- write data to the slave
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR),
(SLAVE_MBASE & MBDR_ADDR), -- write last data word
(MASTR_MBASE & MBCR_ADDR), -- turn off Master's ACK
(MASTR_MBASE & MBCR_ADDR) -- generate STOP
);
-- Declare state names for target state machine
type STATE_TYPE is (IDLE, Tsetup, T1, Tw, T2, DATA_TRS, Thold);
-- Signal Declarations
signal state, next_state : STATE_TYPE;
signal data_out,data_in : std_logic_vector(7 downto 0);
signal write : std_logic; -- write signal
signal go, done : std_logic; -- handshake signals to state machine
signal cycle : integer; -- index into data and address array
signal oe, oe_com : std_logic; -- enables test bench to output data
signal wen_com, rdn_com : std_logic; -- combinatorial versions of we_n and rd_n
signal bsn_com : std_logic; -- combinatorial version of bs_n
signal master_csn_com : std_logic; -- combinatorial version of master_csn
signal slave_csn_com : std_logic; -- combinatorial version of slave_csn
signal rdy_n : std_logic; -- AND of master_rdyn and slave_rdyn
signal cnt : unsigned(3 downto 0); -- counts states
signal cnt_en : std_logic; -- enables counter
signal cnt_rst : std_logic; -- resets counter
begin
-- Define the bi-directional data bus
-- use pulldowns when tri-stated
data_bus <= data_out when oe = '1'
else (others => 'L');
-- ************************************ Clock Process *************************************
-- Process: CREATE_CLK
-- Function: Create 66Mhz clock
CREATE_CLK: process
begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process;
-- *********************************** Main Control Process *********************************
-- define the main controlling process that triggers the state machines
main : process
variable i : integer := 0;
begin
-- initialize control signals
cycle <= 0;
go <= '0';
write <= '0';
-- assert RESET for 100nS
reset <= RESET_ACTIVE;
--wait until clk'event and clk = '1';
--wait until clk'event and clk = '1';
wait for 100 ns;
reset <= not(RESET_ACTIVE);
-- start the process to have the Master transmit data
-- First have to call the state machine to write registers
-- in both master and slave devices, then write to the Master
-- control register to generate the START signal
-- Then write data to the Master's MBCR_MICRO register. Use the signal MCF to determine
-- when a data transfer is complete
-- the cycle signal will index the state machines to the right address and data
-- to be output - The loop below writes the registers, sets the SMBUS header and
-- generates the START signal
-- wait for a clock edge to synchronize everything
wait until clk'event and clk = '1';
write <= '1';
for i in 0 to 5 loop
cycle <= i;
go <= '1';
wait until clk'event and clk ='1';
wait until clk'event and clk = '1';
go <= '0';
wait until done = '1';
end loop;
-- wait for MCF to indicate that transfer is complete
-- then write data to to Masters data register for transfer over SMBUS
for i in 1 to 6 loop
cycle <= cycle + 1;
wait until mcf = '1';
go <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
go <= '0';
wait until done = '1';
end loop;
-- generate stop once tranfer is complete
cycle <= cycle + 1;
wait until mcf = '1';
go <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
go <= '0';
wait until done = '1';
-- now read the status registers
write <= '0';
for i in 0 to 2 loop
cycle <= cycle + 1;
go <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
go <= '0';
wait until done = '1';
end loop;
-- The loop below writes the registers, sets the SMBUS header and
-- generates the START signal for a slave transmit/master receive cycle
write <= '1';
for i in 0 to 2 loop
cycle <= cycle + 1;
go <= '1';
wait until clk'event and clk ='1';
wait until clk'event and clk = '1';
go <= '0';
wait until done = '1';
end loop;
-- wait for MCF to indicate that transfer is complete
-- then write data to to slave's data register for transfer over SMBUS
for i in 1 to 6 loop
cycle <= cycle + 1;
wait until mcf = '1';
go <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
go <= '0';
wait until done = '1';
end loop;
-- turn off Master's ACK
-- wait for MCF to negate again to insure no longer in ACK state
wait until mcf = '0';
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