micro_test.vhd

来自「可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序」· VHDL 代码 · 共 148 行

--***********************************************************************************************
-- micro_test.vhd
--
-- Created: 3/10/00 ALS
--	This file is the top level testbench that instantiates the VHDL component that emulates the
--	micro-controller and instantiates two SMBUS CPLD designs. One of the SMBUS CPLD designs acts as 
--	SMBUS Master, the other as the SMBUS Slave.
-- Revised: 6/27/00 ALS
--	Modified to reflect support of Hitachi SH7750 processor.
-- Revised: 7/12/00 JRH
--	Modified to include a master only device
-- Modified: 11/27/00 JRH
--	Modified to use master/slave devices:  One configured as a master, the other as a slave
--***********************************************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
 

entity MICRO_TEST is
end MICRO_TEST;

architecture archMICRO_TEST of MICRO_TEST is
    signal DATA_BUS: std_logic_vector(7 downto 0);
    signal DATA_MATCH: std_logic;
    signal ADDRESS: std_logic_vector(7 downto 0);
    signal MCF: std_logic;
    signal SDA: std_logic;
    signal CLK: std_logic;
    signal SCL: std_logic;
    signal IRQ: std_logic;
    signal BS_N: std_logic;
    signal MASTER_CS_N: std_logic;
    signal SLAVE_CS_N: std_logic;
    signal RD_N: std_logic;
    signal WE_N: std_logic;
    signal RD_WRN: std_logic;
    signal MASTER_RDYN: std_logic;
    signal SLAVE_RDYN: std_logic;
    signal SLAVE_MCF: std_logic;
    signal RESET: std_logic;
    
    component MICRO_TB
        port(
             IRQ: IN STD_LOGIC;
             MCF: IN STD_LOGIC;
             MASTER_CS_N: OUT STD_LOGIC;
	     SLAVE_CS_N: OUT STD_LOGIC;
             BS_N: OUT STD_LOGIC;
             RD_N: OUT STD_LOGIC;
	     WE_N: OUT STD_LOGIC;
	     RD_WRN: OUT STD_LOGIC;
	     MASTER_RDYN: IN STD_LOGIC;
	     SLAVE_RDYN: IN STD_LOGIC;
             ADDRESS: OUT STD_LOGIC_VECTOR(7 downto 0);
             RESET: INOUT STD_LOGIC;
             CLK: INOUT STD_LOGIC;
             DATA_MATCH: OUT STD_LOGIC;
             DATA_BUS: INOUT STD_LOGIC_VECTOR(7 downto 0));
    end component;

    component SMBUS
        port(SDA: INOUT STD_LOGIC;
             SCL: INOUT STD_LOGIC;
             ADDR_BUS: IN STD_LOGIC_VECTOR(7 downto 0);
             DATA_BUS: INOUT STD_LOGIC_VECTOR(7 downto 0);
             CS_N: IN STD_LOGIC;
             BS_N: IN STD_LOGIC;
             RD_N: IN STD_LOGIC;
             WE_N: IN STD_LOGIC;
	     RD_WRN: IN STD_LOGIC;
	     RDY_N: OUT STD_LOGIC;
             IRQ: OUT STD_LOGIC;
             MCF: INOUT STD_LOGIC;
             CLK: IN STD_LOGIC;
             RESET: IN STD_LOGIC);
    end component;

    component PULLUP
        port(v101: OUT std_logic);
    end component;
    
begin
    micro: MICRO_TB
        port map(
                 IRQ => IRQ,
                 MCF => MCF,
                 MASTER_CS_N => MASTER_CS_N,
		 SLAVE_CS_N => SLAVE_CS_N,
                 BS_N => BS_N,
                 RD_N => RD_N,
		 WE_N => WE_N,
		 RD_WRN => RD_WRN,
		 MASTER_RDYN => MASTER_RDYN,
		 SLAVE_RDYN => SLAVE_RDYN,
                 ADDRESS => ADDRESS,
                 RESET => RESET,
                 CLK => CLK,
                 DATA_MATCH => DATA_MATCH,
                 DATA_BUS => DATA_BUS);
    
    MASTER: SMBUS
        port map(SDA => SDA,
                 SCL => SCL,
                 ADDR_BUS => ADDRESS,
                 DATA_BUS => DATA_BUS,
                 CS_N => MASTER_CS_N,
                 BS_N => BS_N,
                 RD_N => RD_N,
		 WE_N => WE_N,
		 RD_WRN => RD_WRN,
		 RDY_N => MASTER_RDYN,
                 IRQ => IRQ,
                 MCF => MCF,
                 CLK => CLK,
                 RESET => RESET);
    
    SLAVE: SMBUS
        port map(SDA => SDA,
                 SCL => SCL,
                 ADDR_BUS => ADDRESS,
                 DATA_BUS => DATA_BUS,
                 CS_N => SLAVE_CS_N,
                 BS_N => BS_N,
                 RD_N => RD_N,
		 WE_N => WE_N,
		 RD_WRN => RD_WRN,
		 RDY_N => SLAVE_RDYN,
                 IRQ => IRQ,
                 MCF => SLAVE_MCF,
                 CLK => CLK,
                 RESET => RESET);
    
    v109: PULLUP
        port map(v101 => SCL);
    
    v110: PULLUP
        port map(v101 => SDA);
    
    
    v112: PULLUP
        port map(v101 => IRQ);
    
    
end archMICRO_TEST;