analyzer.prt

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

clk[0/0] 
BCTpts[1] ct0:350 
Signal[20] [SP_D9(391),SP_D9(T16)] [SP_A1(T17)] [SP_A2(R16)] [SP_A3(R17)] [SP_A6(R19)] [BANK4(387)]  
           [CNT_DWN4(386)] [TRIGGER4(385)] [CNT_DWN12(384)] [E_0_xpla_dummy_o_64(383)] [TRIGGER12(382)]  
           [CNT_DWN2(392)] [TRIGGER2(390)] [CNT_DWN3(389)] [TRIGGER3(388)] [CNT_DWN5(381)] [TRIGGER5(380)]  
           [CNT_DWN6(379)] [TRIGGER6(378)] [CNT_DWN7(377)] 
FbNand[ 0] 
----------------- B l o c k 7 ------------------
PLApt(35/48), Fanin(36/36), Clk(0/2), Bct(1/8), Pin(6/10), Mcell(16/16), FbNand(0/8)
PLApts[35/35] 350 313 318 333 314 319 334 316 320 335 315 328 311 326 15 208 211 207 210 213 216 212 215 237 
              240 235 239 234 238 244 247 242 246 241 245
Fanins[36] SP_A1.p D_0_TRIGADR_RD0.n IN_STATUS0.n D0.p N_PZ_5587.n N_PZ_5596.n D_0_TRIGADR_RD1.n IN_STATUS1.n 
           D1.p D_0_TRIGADR_RD2.n IN_STATUS2.n D2.p D_0_TRIGADR_RD10.n D10.p D_0_TRIGADR_RD8.n D8.p 
           SP_RESETn.p SP_A4.p SP_A19.p SP_A2.p SP_A3.p SP_CS1n.p CNT_DWN8.n SP_D8.p TRIGGER8.n CNT_DWN9.n 
           SP_D9.p TRIGGER9.n E_0_xpla_dummy_o_66.n SP_D13.p SELCLK0.n TRIGGER13.n E_0_xpla_dummy_o_68.n 
           SP_D14.p SELCLK1.n TRIGGER14.n
clk[0/0] 
BCTpts[1] ct0:350 
Signal[16] [SP_D0(407),SP_D0(V16)] [SP_D1(397),SP_D1(W15)] [SP_D2(406),SP_D2(T15)] [SP_D10(404),SP_D10(U15)]  
           [SP_D8(405),SP_D8(V15)] [RESET_MEMn(393),RESET_MEMn(T13)] [CNT_DWN8(403)] [TRIGGER8(402)]  
           [CNT_DWN9(401)] [TRIGGER9(400)] [E_0_xpla_dummy_o_66(399)] [SELCLK0(398)] [TRIGGER13(408)]  
           [E_0_xpla_dummy_o_68(396)] [SELCLK1(395)] [TRIGGER14(394)] 
FbNand[ 0] 
----------------- B l o c k 8 ------------------
PLApt(18/48), Fanin(33/36), Clk(0/2), Bct(3/8), Pin(8/10), Mcell(16/16), FbNand(0/8)
PLApts[18/18] 7 346 347 19 249 253 248 252 202 205 192 193 194 153 348 6 64 65
Fanins[33] SP_OEn.p SP_A19.p SP_CS1n.p SP_A4.p SP_A1.p SP_A2.p SP_A3.p SELCLK2.n SP_D15.p TRIGGER15.n 
           TRIGGER7.n SP_D7.p CNT_DWN12.n IO14.n C_0_DWN_OUT.n C_0_N133030.n C_0_N133028.n C_0_N133026.n 
           C_0_N133024.n C_0_N133022.n C_0_N133020.n C_0_N133018.n C_0_N133062.n C_0_N133060.n C_0_N133058.n 
           C_0_N133056.n C_0_N133054.n C_0_N133052.n C_0_DWN_CLK.n CH_IN2.p N_PZ_5597.n INPUT_HILO.n RAM_D2.n
clk[0/0] 
BCTpts[3] ct4:7 ct5:346 ct6:347 
Signal[24] [IN_STATUS0,CH_IN0(B1)] [IN_STATUS1,CH_IN1(C3)] [IN_STATUS2,CH_IN2(A4)] [IN_STATUS3,CH_IN3(B5)]  
           [IN_STATUS4,CH_IN4(C5)] [IN_STATUS5,CH_IN5(A5)] [IN_STATUS6,CH_IN6(E6)] [IN_STATUS7,CH_IN7(D6)]  
           [N_PZ_5587(419)] [SELCLK2(418)] [TRIGGER15(417)] [TRIGGER7(416)] [C_0_N133052(415)]  
           [B_0_SAMPL_CLK(414)] [RAM_D10(424)] [RAM_D2(423)] 
FbNand[ 0] 
----------------- B l o c k 9 ------------------
PLApt(30/48), Fanin(36/36), Clk(0/2), Bct(4/8), Pin(7/10), Mcell(15/16), FbNand(0/8)
PLApts[30/30] 131 5022 345 349 251 254 56 300 51 52 53 362 378 379 364 369 365 370 366 371 363 380 381 361 
              376 377 360 374 375 368
Fanins[36] SP_A4.p SP_A19.p SP_A1.p SP_A2.p SP_A3.p SP_CS1n.p IO14.n SP_D15.p B_0_N133030.n B_0_N133028.n 
           B_0_N133026.n B_0_N133024.n B_0_N133022.n B_0_N133020.n B_0_N133018.n B_0_N133062.n B_0_N133060.n 
           B_0_N133058.n B_0_N139394.n B_0_N139401.n IO13.n B_0_N177842.n SRAM_CS1n.n E_0_xpla_dummy_o_64.n 
           E_0_xpla_dummy_o_66.n E_0_xpla_dummy_o_68.n SP_D10.p N_PZ_5586.n N_PZ_5599.n B_0_xpla_dummy_o_7.n 
           B_0_xpla_dummy_o_8.n B_0_xpla_dummy_o_9.n B_0_xpla_dummy_o_10.n SP_D11.p SP_D9.p SP_D8.p
clk[0/0] 
BCTpts[4] ct0:131 ct1:5022 ct4:345 ct5:349 
Signal[15] [IO14(429),IO14(E4)] [IO13(428),IO13(E2)] [IO15(436),IO15(E1)] [LED_0(437),LED_0(F5)]  
           [LED_1(438),LED_1(F3)] [LED_2(439),LED_2(F4)] [LED_3(440),LED_3(G3)] [B_0_N139401(435)]  
           [B_0_xpla_dummy_o_8(434)] [B_0_xpla_dummy_o_9(433)] [B_0_xpla_dummy_o_10(432)]  
           [B_0_xpla_dummy_o_7(431)] [B_0_N139394(430)] [B_0_N133058(427)] [B_0_N133030(426)] 
FbNand[ 0] 
----------------- B l o c k 10 ------------------
PLApt(30/48), Fanin(25/36), Clk(0/2), Bct(1/8), Pin(9/10), Mcell(16/16), FbNand(0/8)
PLApts[30/30] 346 91 224 94 229 97 236 100 243 103 250 69 285 72 292 75 297 78 204 70 71 73 74 76 77 79 80 10 
              12 13
Fanins[25] IO14.n RAM_D11.n SP_D11.p RAM_D12.n SP_D12.p RAM_D13.n SP_D13.p RAM_D14.n SP_D14.p RAM_D15.n 
           SP_D15.p RAM_D4.n SP_D4.p RAM_D5.n SP_D5.p RAM_D6.n SP_D6.p RAM_D7.n SP_D7.p CH_IN4.p INPUT_HILO.n 
           N_PZ_5597.n CH_IN5.p CH_IN6.p CH_IN7.p
clk[0/0] 
BCTpts[1] ct4:346 
Signal[16] [D11(455),D11(D10)] [D12(453),D12(C9)] [D13(452),D13(B8)] [D14(442),D14(C7)] [D15(443),D15(B7)]  
           [D4(456),D4(C10)] [D5(445),D5(C8)] [D6(441),D6(D7)] [D7(444),D7(A7)] [RAM_D4(454)] [RAM_D5(451)]  
           [RAM_D6(450)] [RAM_D7(449)] [RAM_D12(448)] [RAM_D13(447)] [RAM_D14(446)] 
FbNand[ 0] 
----------------- B l o c k 11 ------------------
PLApt(25/48), Fanin(25/36), Clk(0/2), Bct(2/8), Pin(6/10), Mcell(16/16), FbNand(0/8)
PLApts[25/25] 346 349 42 55 44 11 58 59 3 61 62 4 67 68 9 14 21 150 152 352 382 383 353 384 385
Fanins[25] SP_WEn.p IO14.n INPUT_HILO.n SP_CS1n.p SP_A19.p CH_IN0.p RAM_D0.n N_PZ_5597.n CH_IN1.p RAM_D1.n 
           CH_IN3.p RAM_D3.n CH_IN7.p SELCLK1.n SELCLK0.n SYS_CLK.p C_0_SYS_CLK2.n C_0_SYS_CLK4.n 
           B_0_N133030.n B_0_N133028.n SP_D0.p N_PZ_5586.n N_PZ_5599.n B_0_N133026.n SP_D1.p
clk[0/0] 
BCTpts[2] ct4:346 ct5:349 
Signal[16] [RWn(469),RWn(J2)] [SRAM_CS1n(471),SRAM_CS1n(K2)] [A18(458),A18(G1)]  
           [FLASH_W_PROTECTn(468),FLASH_W_PROTECTn(H2)] [SRAM_LOW_BYTEn(472),SRAM_LOW_BYTEn(K3)]  
           [SRAM_UPPER_BYTEn(470),SRAM_UPPER_BYTEn(J3)] [RAM_D0(467)] [RAM_D8(466)] [RAM_D1(465)]  
           [RAM_D9(464)] [RAM_D3(463)] [RAM_D11(462)] [RAM_D15(461)] [C_0_DWN_CLK(460)] [B_0_N133028(459)]  
           [B_0_N133026(457)] 
FbNand[ 0] 
----------------- B l o c k 12 ------------------
PLApt(36/48), Fanin(36/36), Clk(0/2), Bct(1/8), Pin(10/10), Mcell(15/16), FbNand(0/8)
PLApts[36/36] 349 41 108 35 48 38 50 43 110 24 112 26 114 28 116 30 118 32 120 23 124 354 386 387 355 388 389 
              356 390 391 357 392 393 358 394 395
Fanins[36] IO14.n SP_A2.p RAM_A1.n SP_A16.p BANK2.n SP_A18.p BANK4.n SP_A3.p RAM_A2.n SP_A4.p RAM_A3.n 
           SP_A5.p RAM_A4.n SP_A6.p RAM_A5.n SP_A7.p RAM_A6.n SP_A8.p RAM_A7.n SP_A10.p RAM_A9.n 
           B_0_N133030.n B_0_N133028.n B_0_N133026.n B_0_N133024.n SP_D2.p N_PZ_5586.n N_PZ_5599.n 
           B_0_N133022.n SP_D3.p B_0_N133020.n SP_D4.p B_0_N133018.n SP_D5.p B_0_N133062.n SP_D6.p
clk[0/0] 
BCTpts[1] ct4:349 
Signal[15] [A1(473),A1(W10)] [A15(488),A15(T6)] [A17(484),A17(W7)] [A2(474),A2(T9)] [A3(475),A3(U9)]  
           [A4(476),A4(T8)] [A5(485),A5(V7)] [A6(486),A6(U7)] [A7(477),A7(T7)] [A9(487),A9(W6)]  
           [B_0_N133024(483)] [B_0_N133022(482)] [B_0_N133020(481)] [B_0_N133018(480)] [B_0_N133062(479)] 
FbNand[ 0] 
----------------- B l o c k 13 ------------------
PLApt(4/48), Fanin(12/36), Clk(0/2), Bct(1/8), Pin(0/10), Mcell(1/16), FbNand(0/8)
PLApts[4/4] 349 359 372 373
Fanins[12] B_0_N133030.n B_0_N133028.n B_0_N133026.n B_0_N133024.n B_0_N133022.n B_0_N133020.n B_0_N133018.n 
           B_0_N133062.n B_0_N133060.n SP_D7.p N_PZ_5586.n N_PZ_5599.n
clk[0/0] 
BCTpts[1] ct4:349 
Signal[ 1] [B_0_N133060(491)] 
FbNand[ 0] 
----------------- B l o c k 14 ------------------
PLApt(18/48), Fanin(19/36), Clk(0/2), Bct(0/8), Pin(10/10), Mcell(10/16), FbNand(0/8)
PLApts[18/18] 40 106 25 126 27 128 29 130 31 46 33 47 36 49 34 122 17 1
Fanins[19] IO14.n SP_A1.p RAM_A0.n SP_A11.p RAM_A10.n SP_A12.p RAM_A11.n SP_A13.p RAM_A12.n SP_A14.p BANK0.n 
           SP_A15.p BANK1.n SP_A17.p BANK3.n SP_A9.p RAM_A8.n SP_A20.p SP_A21.p
clk[0/0] 
BCTpts[0] 
Signal[10] [A0(509),A0(T5)] [A10(516),A10(V5)] [A11(508),A11(W5)] [A12(518),A12(W4)] [A13(520),A13(W3)]  
           [A14(506),A14(U6)] [A16(507),A16(R6)] [A8(505),A8(V6)] [A19(517),A19(U5)] [A20(519),A20(U4)] 
FbNand[ 0] 
----------------- B l o c k 15 ------------------