analyzer.prt

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

Gct[0] comes from: block 0's CT7 (pt 16)
Gct[1] comes from: block 1's CT7 (pt 5351)
Gct[3] comes from: block 2's CT7 (pt 149)

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|  P a r t i t i o n i n g . . .  , Seed = 0, Approach = 0, state = 1, GrpAlg=0  |
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Check Pin-locking? Yes (Approach = -1); Timing-driven partition? No

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|  P a r t i t i o n    S u c c e e d  |
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0 Group(s)

ClkInput[1]: SYS_CLK(A10, sclk) 
GOE: 5351
GRST: 149
GACLK: 16
----------------- B l o c k 0 ------------------
PLApt(19/48), Fanin(21/36), Clk(1/2), Bct(6/8), Pin(9/10), Mcell(16/16), FbNand(0/8)
PLApts[19/19] 350 5022 56 151 341 16 309 317 148 105 107 136 137 138 139 140 141 142 143
Fanins[21] SP_WEn.p SP_A1.p IO14.n D15.p N_PZ_5587.n N_PZ_5596.n A_0_QA.n C_0_SYS_CLK2.n RAM_A0.n IO13.n 
           RAM_A1.n INPUT_HILO.n B_0_ACQ_BEGIN.n B_0_SAMPL_CLK.n RAM_A2.n RAM_A3.n RAM_A4.n RAM_A5.n RAM_A6.n 
           RAM_A7.n RAM_A8.n
clk[1/1] SYS_CLK 
BCTpts[6] ct0:350 ct1:5022 ct4:56 ct5:151 ct6:341 ct7:16 
Signal[23] [SP_D15(283),SP_D15(F15)] [SP_IRQn(295),SP_IRQn(G19)] [SP_A10(F17)] [SP_A14(E18)] [SP_A19(E19)]  
           [SP_A20(F19)] [SP_CS1n(G16)] [SP_OEn(G17)] [SP_WEn(F18)] [C_0_SYS_CLK2(291)] [A_0_QA(290)]  
           [A_0_xpla_dummy_o_1(289)] [C_0_SYS_CLK4(288)] [D_0_TRIGADR_RD0(287)] [D_0_TRIGADR_RD1(286)]  
           [RAM_A2(296)] [RAM_A3(294)] [RAM_A4(293)] [RAM_A5(292)] [RAM_A6(285)] [RAM_A7(284)] [RAM_A8(282)]  
           [RAM_A9(281)] 
FbNand[ 0] 
----------------- B l o c k 1 ------------------
PLApt(33/48), Fanin(34/36), Clk(0/2), Bct(3/8), Pin(10/10), Mcell(16/16), FbNand(0/8)
PLApts[33/33] 350 56 5351 302 321 336 304 322 337 306 323 338 308 324 339 310 325 340 301 329 303 330 305 331 
              307 332 125 127 129 109 111 113 115
Fanins[34] N_PZ_5595.n SP_A1.p D_0_TRIGADR_RD3.n IN_STATUS3.n D3.p N_PZ_5587.n N_PZ_5596.n D_0_TRIGADR_RD4.n 
           IN_STATUS4.n D4.p D_0_TRIGADR_RD5.n IN_STATUS5.n D5.p D_0_TRIGADR_RD6.n IN_STATUS6.n D6.p 
           D_0_TRIGADR_RD7.n IN_STATUS7.n D7.p D_0_TRIGADR_RD11.n D11.p D_0_TRIGADR_RD12.n D12.p 
           D_0_TRIG_HILO.n D13.p IO13.n D14.p RAM_A10.n RAM_A11.n RAM_A12.n RAM_A2.n RAM_A3.n RAM_A4.n 
           RAM_A5.n
clk[0/0] 
BCTpts[3] ct0:350 ct4:56 ct7:5351 
Signal[17] [SP_D3(311),SP_D3(D15)] [SP_D4(310),SP_D4(E15)] [SP_D5(312),SP_D5(A15)] [SP_D6(301),SP_D6(A17)]  
           [SP_D7(300),SP_D7(A18)] [SP_D11(308),SP_D11(C16)] [SP_D12(309),SP_D12(A16)]  
           [SP_D13(299),SP_D13(B17)] [SP_D14(298),SP_D14(B18)] [SP_CS0n(B19)] [D_0_TRIGADR_RD10(307)]  
           [D_0_TRIGADR_RD11(306)] [D_0_TRIGADR_RD12(305)] [D_0_TRIGADR_RD2(304)] [D_0_TRIGADR_RD3(303)]  
           [D_0_TRIGADR_RD4(302)] [D_0_TRIGADR_RD5(297)] 
FbNand[ 0] 
----------------- B l o c k 2 ------------------
PLApt(25/48), Fanin(24/36), Clk(0/2), Bct(5/8), Pin(7/10), Mcell(16/16), FbNand(0/8)
PLApts[25/25] 341 56 149 341 149 117 119 121 144 145 146 147 135 134 123 54 133 132 343 344 342 367 39 42 45
Fanins[24] IO14.n A_0_xpla_dummy_o_1.n RAM_A6.n IO13.n RAM_A7.n RAM_A8.n INPUT_HILO.n RAM_A0.n RAM_A1.n 
           RAM_A2.n RAM_A3.n RAM_A4.n RAM_A5.n RAM_A9.n B_0_ACQ_BEGIN.n B_0_SAMPL_CLK.n RAM_A10.n RAM_A11.n 
           RAM_A12.n SP_WEn.p N_PZ_5586.n SP_CS0n.p SP_A19.p SP_CS1n.p
clk[0/0] 
BCTpts[5] ct0:341 ct4:56 ct5:149 ct6:341 ct7:149 
Signal[23] [SP_A11(H17)] [SP_A15(K18)] [SP_A16(H19)] [SP_A17(L16)] [SP_A21(H18)] [SP_A8(K17)] [SP_A9(J17)]  
           [D_0_TRIGADR_RD6(323)] [D_0_TRIGADR_RD7(322)] [D_0_TRIGADR_RD8(321)] [RAM_A10(320)]  
           [RAM_A11(319)] [RAM_A12(318)] [B_0_xpla_dummy_o_11(328)] [RAM_A1(327)] [RAM_A0(326)]  
           [D_0_TRIGADR_RD9(325)] [D_0_TRIG_HILO(324)] [INPUT_HILO(317)] [B_0_ACQ_BEGIN(316)]  
           [N_PZ_5597(315)] [N_PZ_5599(314)] [N_PZ_5595(313)] 
FbNand[ 0] 
----------------- B l o c k 3 ------------------
PLApt(30/48), Fanin(29/36), Clk(0/2), Bct(0/8), Pin(9/10), Mcell(16/16), FbNand(0/8)
PLApts[30/30] 57 257 60 264 88 219 63 271 66 278 82 209 85 214 37 2 8 18 258 261 265 268 272 275 279 282 256 
              260 263 267
Fanins[29] IO14.n RAM_D0.n SP_D0.p RAM_D1.n SP_D1.p RAM_D10.n SP_D10.p RAM_D2.n SP_D2.p RAM_D3.n SP_D3.p 
           RAM_D8.n SP_D8.p RAM_D9.n SP_D9.p SP_OEn.p SP_CS0n.p SP_CS1n.p SP_A4.p SP_A19.p SP_A1.p SP_A2.p 
           SP_A3.p BANK0.n BANK1.n BANK2.n BANK3.n CNT_DWN0.n CNT_DWN1.n
clk[0/0] 
BCTpts[0] 
Signal[16] [D0(331),D0(A14)] [D1(333),D1(B13)] [D10(343),D10(B12)] [D2(344),D2(D12)] [D3(341),D3(A12)]  
           [D8(332),D8(C13)] [D9(340),D9(A13)] [OEn(330),OEn(D14)] [FLASH_CS0n(329),FLASH_CS0n(E14)]  
           [N_PZ_5596(342)] [BANK0(339)] [BANK1(338)] [BANK2(337)] [BANK3(336)] [CNT_DWN0(335)]  
           [CNT_DWN1(334)] 
FbNand[ 0] 
----------------- B l o c k 4 ------------------
PLApt(46/48), Fanin(32/36), Clk(1/2), Bct(1/8), Pin(7/10), Mcell(16/16), FbNand(0/8)
PLApts[46/46] 347 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 
              179 180 181 182 183 184 185 186 187 188 189 190 191 195 196 197 198 200 201 154 155 199
Fanins[32] CNT_DWN0.n SELCLK2.n IO14.n C_0_DWN_OUT.n C_0_N133030.n C_0_DWN_CLK.n CNT_DWN1.n C_0_N133028.n 
           CNT_DWN2.n C_0_N133026.n CNT_DWN3.n C_0_N133024.n CNT_DWN4.n C_0_N133022.n CNT_DWN5.n 
           C_0_N133020.n CNT_DWN6.n C_0_N133018.n CNT_DWN7.n C_0_N133062.n CNT_DWN8.n C_0_N133060.n 
           CNT_DWN9.n C_0_N133058.n CNT_DWN10.n C_0_N133056.n CNT_DWN11.n C_0_N133054.n C_0_N133052.n 
           C_0_N133234.n C_0_N133197.n C_0_xpla_dummy_o_3.n
clk[1/1] SYS_CLK 
BCTpts[1] ct4:347 
Signal[23] [SP_A12(M18)] [SP_A13(L17)] [SP_A18(M17)] [SP_A4(N16)] [SP_A5(M16)] [SP_A7(N18)] [SP_RESETn(N17)]  
           [C_0_N133030(347)] [C_0_N133028(355)] [C_0_N133026(354)] [C_0_N133024(353)] [C_0_N133022(352)]  
           [C_0_N133020(351)] [C_0_N133018(350)] [C_0_N133062(360)] [C_0_N133060(359)] [C_0_N133058(358)]  
           [C_0_N133056(357)] [C_0_N133054(356)] [C_0_N133234(349)] [C_0_N133197(348)]  
           [C_0_xpla_dummy_o_3(346)] [C_0_DWN_OUT(345)] 
FbNand[ 0] 
----------------- B l o c k 5 ------------------
PLApt(29/48), Fanin(36/36), Clk(0/2), Bct(0/8), Pin(0/10), Mcell(8/16), FbNand(0/8)
PLApts[29/29] 81 83 84 86 87 89 90 92 93 95 96 98 99 101 102 104 255 259 262 266 217 220 218 221 222 225 223 
              226 20
Fanins[36] TRIGGER0.n TRIGGER1.n TRIGGER2.n TRIGGER3.n TRIGGER4.n TRIGGER5.n TRIGGER6.n TRIGGER7.n TRIGGER8.n 
           TRIGGER9.n TRIGGER10.n TRIGGER11.n TRIGGER12.n TRIGGER13.n TRIGGER14.n TRIGGER15.n RAM_D8.n 
           RAM_D9.n RAM_D10.n RAM_D11.n RAM_D12.n RAM_D13.n RAM_D14.n RAM_D15.n SP_A4.p SP_A19.p SP_A1.p 
           SP_A2.p SP_A3.p SP_CS1n.p SP_D0.p SP_D1.p SP_D10.p CNT_DWN10.n SP_D11.p CNT_DWN11.n
clk[0/0] 
BCTpts[0] 
Signal[ 8] [B_0_N177842(371)] [TRIGGER0(370)] [TRIGGER1(369)] [TRIGGER10(368)] [CNT_DWN10(367)]  
           [TRIGGER11(366)] [CNT_DWN11(376)] [N_PZ_5586(375)] 
FbNand[ 0] 
----------------- B l o c k 6 ------------------
PLApt(33/48), Fanin(32/36), Clk(0/2), Bct(1/8), Pin(5/10), Mcell(16/16), FbNand(0/8)
PLApts[33/33] 350 312 327 286 289 284 288 283 287 228 232 230 233 227 231 270 274 269 273 277 281 276 280 291 
              294 290 293 296 299 295 298 203 206
Fanins[32] SP_A1.p D_0_TRIGADR_RD9.n D9.p N_PZ_5587.n N_PZ_5596.n SP_A4.p SP_A19.p SP_A2.p SP_A3.p SP_CS1n.p 
           BANK4.n SP_D4.p CNT_DWN4.n TRIGGER4.n CNT_DWN12.n SP_D12.p E_0_xpla_dummy_o_64.n TRIGGER12.n 
           CNT_DWN2.n SP_D2.p TRIGGER2.n CNT_DWN3.n SP_D3.p TRIGGER3.n CNT_DWN5.n SP_D5.p TRIGGER5.n 
           CNT_DWN6.n SP_D6.p TRIGGER6.n CNT_DWN7.n SP_D7.p