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📄 analyzer.ann

📁 可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计
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"XPLAOPT Version 3.43
"Device Name: XCR3256XL-10CS280
"Created on:  Aug 13 22:40:28 2001

MODULE LogicAnalyzer

"******** 1 Clock/Input Pin(s) *********************************************
SYS_CLK             PIN  A10;
"******** 34 Input Pin(s) **************************************************
CH_IN0              PIN  B1;
CH_IN1              PIN  C3;
CH_IN2              PIN  A4;
CH_IN3              PIN  B5;
CH_IN4              PIN  C5;
CH_IN5              PIN  A5;
CH_IN6              PIN  E6;
CH_IN7              PIN  D6;
SP_A1               PIN  T17;
SP_A10              PIN  F17;
SP_A11              PIN  H17;
SP_A12              PIN  M18;
SP_A13              PIN  L17;
SP_A14              PIN  E18;
SP_A15              PIN  K18;
SP_A16              PIN  H19;
SP_A17              PIN  L16;
SP_A18              PIN  M17;
SP_A19              PIN  E19;
SP_A2               PIN  R16;
SP_A20              PIN  F19;
SP_A21              PIN  H18;
SP_A3               PIN  R17;
SP_A4               PIN  N16;
SP_A5               PIN  M16;
SP_A6               PIN  R19;
SP_A7               PIN  N18;
SP_A8               PIN  K17;
SP_A9               PIN  J17;
SP_CS0n             PIN  B19;
SP_CS1n             PIN  G16;
SP_OEn              PIN  G17;
SP_RESETn           PIN  N17;
SP_WEn              PIN  F18;
"******** 69 Output Pin(s) *************************************************
A0                  PIN  T5;
A1                  PIN  W10;
A10                 PIN  V5;
A11                 PIN  W5;
A12                 PIN  W4;
A13                 PIN  W3;
A14                 PIN  U6;
A15                 PIN  T6;
A16                 PIN  R6;
A17                 PIN  W7;
A18                 PIN  G1;
A19                 PIN  U5;
A2                  PIN  T9;
A20                 PIN  U4;
A3                  PIN  U9;
A4                  PIN  T8;
A5                  PIN  V7;
A6                  PIN  U7;
A7                  PIN  T7;
A8                  PIN  V6;
A9                  PIN  W6;
D0                  PIN  A14;
D1                  PIN  B13;
D10                 PIN  B12;
D11                 PIN  D10;
D12                 PIN  C9;
D13                 PIN  B8;
D14                 PIN  C7;
D15                 PIN  B7;
D2                  PIN  D12;
D3                  PIN  A12;
D4                  PIN  C10;
D5                  PIN  C8;
D6                  PIN  D7;
D7                  PIN  A7;
D8                  PIN  C13;
D9                  PIN  A13;
FLASH_CS0n          PIN  E14;
FLASH_W_PROTECTn    PIN  H2;
IO13                PIN  E2;
IO14                PIN  E4;
IO15                PIN  E1;
LED_0               PIN  F5;
LED_1               PIN  F3;
LED_2               PIN  F4;
LED_3               PIN  G3;
OEn                 PIN  D14;
RESET_MEMn          PIN  T13;
RWn                 PIN  J2;
SP_D0               PIN  V16;
SP_D1               PIN  W15;
SP_D10              PIN  U15;
SP_D11              PIN  C16;
SP_D12              PIN  A16;
SP_D13              PIN  B17;
SP_D14              PIN  B18;
SP_D15              PIN  F15;
SP_D2               PIN  T15;
SP_D3               PIN  D15;
SP_D4               PIN  E15;
SP_D5               PIN  A15;
SP_D6               PIN  A17;
SP_D7               PIN  A18;
SP_D8               PIN  V15;
SP_D9               PIN  T16;
SP_IRQn             PIN  G19;
SRAM_CS1n           PIN  K2;
SRAM_LOW_BYTEn      PIN  K3;
SRAM_UPPER_BYTEn    PIN  J3;
"******** 131 Node(s) ******************************************************
A_0_QA              NODE 290;
A_0_xpla_dummy_o_1  NODE 289;
BANK0               NODE 339;
BANK1               NODE 338;
BANK2               NODE 337;
BANK3               NODE 336;
BANK4               NODE 387;
B_0_ACQ_BEGIN       NODE 316;
B_0_N133018         NODE 480;
B_0_N133020         NODE 481;
B_0_N133022         NODE 482;
B_0_N133024         NODE 483;
B_0_N133026         NODE 457;
B_0_N133028         NODE 459;
B_0_N133030         NODE 426;
B_0_N133058         NODE 427;
B_0_N133060         NODE 491;
B_0_N133062         NODE 479;
B_0_N139394         NODE 430;
B_0_N139401         NODE 435;
B_0_N177842         NODE 371;
B_0_SAMPL_CLK       NODE 414;
B_0_xpla_dummy_o_10 NODE 432;
B_0_xpla_dummy_o_7  NODE 431;
B_0_xpla_dummy_o_8  NODE 434;
B_0_xpla_dummy_o_9  NODE 433;
CNT_DWN0            NODE 335;
CNT_DWN1            NODE 334;
CNT_DWN10           NODE 367;
CNT_DWN11           NODE 376;
CNT_DWN12           NODE 384;
CNT_DWN2            NODE 392;
CNT_DWN3            NODE 389;
CNT_DWN4            NODE 386;
CNT_DWN5            NODE 381;
CNT_DWN6            NODE 379;
CNT_DWN7            NODE 377;
CNT_DWN8            NODE 403;
CNT_DWN9            NODE 401;
C_0_DWN_CLK         NODE 460;
C_0_DWN_OUT         NODE 345;
C_0_N133018         NODE 350;
C_0_N133020         NODE 351;
C_0_N133022         NODE 352;
C_0_N133024         NODE 353;
C_0_N133026         NODE 354;
C_0_N133028         NODE 355;
C_0_N133030         NODE 347;
C_0_N133052         NODE 415;
C_0_N133054         NODE 356;
C_0_N133056         NODE 357;
C_0_N133058         NODE 358;
C_0_N133060         NODE 359;
C_0_N133062         NODE 360;
C_0_N133197         NODE 348;
C_0_N133234         NODE 349;
C_0_SYS_CLK2        NODE 291;
C_0_SYS_CLK4        NODE 288;
C_0_xpla_dummy_o_3  NODE 346;
D_0_TRIGADR_RD0     NODE 287;
D_0_TRIGADR_RD1     NODE 286;
D_0_TRIGADR_RD10    NODE 307;
D_0_TRIGADR_RD11    NODE 306;
D_0_TRIGADR_RD12    NODE 305;
D_0_TRIGADR_RD2     NODE 304;
D_0_TRIGADR_RD3     NODE 303;
D_0_TRIGADR_RD4     NODE 302;
D_0_TRIGADR_RD5     NODE 297;
D_0_TRIGADR_RD6     NODE 323;
D_0_TRIGADR_RD7     NODE 322;
D_0_TRIGADR_RD8     NODE 321;
D_0_TRIGADR_RD9     NODE 325;
D_0_TRIG_HILO       NODE 324;
E_0_xpla_dummy_o_64 NODE 383;
E_0_xpla_dummy_o_66 NODE 399;
E_0_xpla_dummy_o_68 NODE 396;
INPUT_HILO          NODE 317;
N_PZ_5586           NODE 375;
N_PZ_5587           NODE 419;
N_PZ_5595           NODE 313;
N_PZ_5596           NODE 342;
N_PZ_5597           NODE 315;
N_PZ_5599           NODE 314;
RAM_A0              NODE 326;
RAM_A1              NODE 327;
RAM_A10             NODE 320;
RAM_A11             NODE 319;
RAM_A12             NODE 318;
RAM_A2              NODE 296;
RAM_A3              NODE 294;
RAM_A4              NODE 293;
RAM_A5              NODE 292;
RAM_A6              NODE 285;
RAM_A7              NODE 284;
RAM_A8              NODE 282;
RAM_A9              NODE 281;
RAM_D0              NODE 467;
RAM_D1              NODE 465;
RAM_D10             NODE 424;
RAM_D11             NODE 462;
RAM_D12             NODE 448;
RAM_D13             NODE 447;
RAM_D14             NODE 446;
RAM_D15             NODE 461;
RAM_D2              NODE 423;
RAM_D3              NODE 463;
RAM_D4              NODE 454;
RAM_D5              NODE 451;
RAM_D6              NODE 450;
RAM_D7              NODE 449;
RAM_D8              NODE 466;
RAM_D9              NODE 464;
SELCLK0             NODE 398;
SELCLK1             NODE 395;
SELCLK2             NODE 418;
TRIGGER0            NODE 370;
TRIGGER1            NODE 369;
TRIGGER10           NODE 368;
TRIGGER11           NODE 366;
TRIGGER12           NODE 382;
TRIGGER13           NODE 408;
TRIGGER14           NODE 394;
TRIGGER15           NODE 417;
TRIGGER2            NODE 390;
TRIGGER3            NODE 388;
TRIGGER4            NODE 385;
TRIGGER5            NODE 380;
TRIGGER6            NODE 378;
TRIGGER7            NODE 416;
TRIGGER8            NODE 402;
TRIGGER9            NODE 400;
"******** 8 Input Register Node(s) *****************************************
IN_STATUS0          NODE B1;
IN_STATUS1          NODE C3;
IN_STATUS2          NODE A4;
IN_STATUS3          NODE B5;
IN_STATUS4          NODE C5;
IN_STATUS5          NODE A5;
IN_STATUS6          NODE E6;
IN_STATUS7          NODE D6;


EQUATIONS

"********( A0 )*************************************************************
"PLA 2 pts
A0           = !IO14.Q & SP_A1
               # RAM_A0.Q & IO14.Q;
"********( A1 )*************************************************************
"PLA 2 pts
A1           = !IO14.Q & SP_A2
               # RAM_A1.Q & IO14.Q;
"********( A10 )************************************************************
"PLA 2 pts
A10          = SP_A11 & !IO14.Q
               # RAM_A10.Q & IO14.Q;
"********( A11 )************************************************************
"PLA 2 pts
A11          = !IO14.Q & SP_A12
               # RAM_A11.Q & IO14.Q;
"********( A12 )************************************************************
"PLA 2 pts
A12          = !IO14.Q & SP_A13
               # RAM_A12.Q & IO14.Q;
"********( A13 )************************************************************
"PLA 2 pts
A13          = !IO14.Q & SP_A14
               # BANK0.Q & IO14.Q;
"********( A14 )************************************************************
"PLA 2 pts
A14          = !IO14.Q & SP_A15
               # BANK1.Q & IO14.Q;
"********( A15 )************************************************************
"PLA 2 pts
A15          = !IO14.Q & SP_A16
               # IO14.Q & BANK2.Q;
"********( A16 )************************************************************
"PLA 2 pts
A16          = !IO14.Q & SP_A17

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