analyzer.cxt

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

   <MuxCon NNm="FB2_5_D" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_5_P">
   <MuxCon NNm="FB2_5_P" Port="Z"/>
   <MuxCon NNm="FB2_5_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB2_5_I">
   <BufCon NNm="FB2_5_I" Port="Z"/>
   <BufCon NNm="SP_D6" Port="I"/>
  </InBuf>
  <OutBuf Nm="FB2_5_O">
   <BufCon NNm="SP_D6" Port="Z"/>
   <BufCon NNm="FB2_5_D" Port="I"/>
   <BufCon NNm="FB2_PT0" Port="OE"/>
  </OutBuf>
  <Or Nm="FB2_5_OR">
   <OrCon NNm="FB2_PT13" Port="I"/>
   <OrCon NNm="FB2_PT14" Port="I"/>
   <OrCon NNm="FB2_PT15" Port="I"/>
   <OrCon NNm="FB2_5_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB2_6">
  <FBMux Nm="FB2_6_N">
   <MuxCon NNm="FB2_6_N" Port="Z"/>
   <MuxCon NNm="FB2_6_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_6_P">
   <MuxCon NNm="FB2_6_P" Port="Z"/>
   <MuxCon NNm="FB2_6_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB2_6_FF">
   <FlopCon NNm="FB2_PT4" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB2_PT18" Port="D"/>
   <FlopCon NNm="FB2_6_Q" Port="Q"/>
  </DFlop>
 </Mc>
 <Mc Nm="FB2_7">
  <FBMux Nm="FB2_7_N">
   <MuxCon NNm="FB2_7_N" Port="Z"/>
   <MuxCon NNm="FB2_7_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_7_P">
   <MuxCon NNm="FB2_7_P" Port="Z"/>
   <MuxCon NNm="FB2_7_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB2_7_FF">
   <FlopCon NNm="FB2_PT4" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB2_PT20" Port="D"/>
   <FlopCon NNm="FB2_7_Q" Port="Q"/>
  </DFlop>
 </Mc>
 <Mc Nm="FB2_8">
  <FBMux Nm="FB2_8_N">
   <MuxCon NNm="FB2_8_N" Port="Z"/>
   <MuxCon NNm="FB2_8_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_8_P">
   <MuxCon NNm="FB2_8_P" Port="Z"/>
   <MuxCon NNm="FB2_8_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB2_8_FF">
   <FlopCon NNm="FB2_PT4" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB2_PT22" Port="D"/>
   <FlopCon NNm="FB2_8_Q" Port="Q"/>
  </DFlop>
 </Mc>
 <Mc Nm="FB2_9">
  <FBMux Nm="FB2_9_N">
   <MuxCon NNm="FB2_9_N" Port="Z"/>
   <MuxCon NNm="FB2_9_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_9_P">
   <MuxCon NNm="FB2_9_P" Port="Z"/>
   <MuxCon NNm="FB2_9_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB2_9_FF">
   <FlopCon NNm="FB2_PT4" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB2_PT24" Port="D"/>
   <FlopCon NNm="FB2_9_Q" Port="Q"/>
  </DFlop>
 </Mc>
 <Mc Nm="FB2_10">
  <FBMux Nm="FB2_10_N">
   <MuxCon NNm="FB2_10_N" Port="Z"/>
   <MuxCon NNm="FB2_10_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_10_P">
   <MuxCon NNm="FB2_10_P" Port="Z"/>
   <MuxCon NNm="FB2_10_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB2_10_FF">
   <FlopCon NNm="FB2_PT4" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB2_PT26" Port="D"/>
   <FlopCon NNm="FB2_10_Q" Port="Q"/>
  </DFlop>
 </Mc>
 <Mc Nm="FB2_11">
  <FBMux Nm="FB2_11_N">
   <MuxCon NNm="FB2_11_N" Port="Z"/>
   <MuxCon NNm="FB2_11_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_11_P">
   <MuxCon NNm="FB2_11_P" Port="Z"/>
   <MuxCon NNm="FB2_11_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB2_11_FF">
   <FlopCon NNm="FB2_PT4" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB2_PT28" Port="D"/>
   <FlopCon NNm="FB2_11_Q" Port="Q"/>
  </DFlop>
 </Mc>
 <Mc Nm="FB2_12">
  <FBMux Nm="FB2_12_N">
   <MuxCon NNm="FB2_12_N" Port="Z"/>
   <MuxCon NNm="FB2_12_D" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_12_P">
   <MuxCon NNm="FB2_12_P" Port="Z"/>
   <MuxCon NNm="FB2_12_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB2_12_I">
   <BufCon NNm="FB2_12_I" Port="Z"/>
   <BufCon NNm="SP_D11" Port="I"/>
  </InBuf>
  <OutBuf Nm="FB2_12_O">
   <BufCon NNm="SP_D11" Port="Z"/>
   <BufCon NNm="FB2_12_D" Port="I"/>
   <BufCon NNm="FB2_PT0" Port="OE"/>
  </OutBuf>
  <Or Nm="FB2_12_OR">
   <OrCon NNm="FB2_PT21" Port="I"/>
   <OrCon NNm="FB2_PT23" Port="I"/>
   <OrCon NNm="FB2_12_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB2_13">
  <FBMux Nm="FB2_13_N">
   <MuxCon NNm="FB2_13_N" Port="Z"/>
   <MuxCon NNm="FB2_13_D" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_13_P">
   <MuxCon NNm="FB2_13_P" Port="Z"/>
   <MuxCon NNm="FB2_13_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB2_13_I">
   <BufCon NNm="FB2_13_I" Port="Z"/>
   <BufCon NNm="SP_D12" Port="I"/>
  </InBuf>
  <OutBuf Nm="FB2_13_O">
   <BufCon NNm="SP_D12" Port="Z"/>
   <BufCon NNm="FB2_13_D" Port="I"/>
   <BufCon NNm="FB2_PT0" Port="OE"/>
  </OutBuf>
  <Or Nm="FB2_13_OR">
   <OrCon NNm="FB2_PT25" Port="I"/>
   <OrCon NNm="FB2_PT27" Port="I"/>
   <OrCon NNm="FB2_13_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB2_14">
  <FBMux Nm="FB2_14_N">
   <MuxCon NNm="FB2_14_N" Port="Z"/>
   <MuxCon NNm="FB2_14_D" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_14_P">
   <MuxCon NNm="FB2_14_P" Port="Z"/>
   <MuxCon NNm="FB2_14_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB2_14_I">
   <BufCon NNm="FB2_14_I" Port="Z"/>
   <BufCon NNm="SP_D4" Port="I"/>
  </InBuf>
  <OutBuf Nm="FB2_14_O">
   <BufCon NNm="SP_D4" Port="Z"/>
   <BufCon NNm="FB2_14_D" Port="I"/>
   <BufCon NNm="FB2_PT0" Port="OE"/>
  </OutBuf>
  <Or Nm="FB2_14_OR">
   <OrCon NNm="FB2_PT5" Port="I"/>
   <OrCon NNm="FB2_PT6" Port="I"/>
   <OrCon NNm="FB2_PT9" Port="I"/>
   <OrCon NNm="FB2_14_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB2_15">
  <FBMux Nm="FB2_15_N">
   <MuxCon NNm="FB2_15_N" Port="Z"/>
   <MuxCon NNm="FB2_15_D" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_15_P">
   <MuxCon NNm="FB2_15_P" Port="Z"/>
   <MuxCon NNm="FB2_15_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB2_15_I">
   <BufCon NNm="FB2_15_I" Port="Z"/>
   <BufCon NNm="SP_D3" Port="I"/>
  </InBuf>
  <OutBuf Nm="FB2_15_O">
   <BufCon NNm="SP_D3" Port="Z"/>
   <BufCon NNm="FB2_15_D" Port="I"/>
   <BufCon NNm="FB2_PT0" Port="OE"/>
  </OutBuf>
  <Or Nm="FB2_15_OR">
   <OrCon NNm="FB2_PT1" Port="I"/>
   <OrCon NNm="FB2_PT2" Port="I"/>
   <OrCon NNm="FB2_PT3" Port="I"/>
   <OrCon NNm="FB2_15_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB2_16">
  <FBMux Nm="FB2_16_N">
   <MuxCon NNm="FB2_16_N" Port="Z"/>
   <MuxCon NNm="FB2_16_D" Port="I"/>
  </FBMux>
  <MCMux Nm="FB2_16_P">
   <MuxCon NNm="FB2_16_P" Port="Z"/>
   <MuxCon NNm="FB2_16_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB2_16_I">
   <BufCon NNm="FB2_16_I" Port="Z"/>
   <BufCon NNm="SP_D5" Port="I"/>
  </InBuf>
  <OutBuf Nm="FB2_16_O">
   <BufCon NNm="SP_D5" Port="Z"/>
   <BufCon NNm="FB2_16_D" Port="I"/>
   <BufCon NNm="FB2_PT0" Port="OE"/>
  </OutBuf>
  <Or Nm="FB2_16_OR">
   <OrCon NNm="FB2_PT10" Port="I"/>
   <OrCon NNm="FB2_PT11" Port="I"/>
   <OrCon NNm="FB2_PT12" Port="I"/>
   <OrCon NNm="FB2_16_D" Port="Z"/>
  </Or>
 </Mc>
 <SDot Nm="UCT1">
  <SDotO NNm="UCT1"/>
  <SDotI NNm="FB2_PT7"/>
 </SDot>
</Lb>
<Lb Nm="FB3">
 <LbT Nm="FB3_PT0" PtT="CT">
  <LbTO NNm="FB3_PT0"/>
  <!-- B_0_SAMPL_CLK_n -->
  <LbTI NNm="FB9_6_N"/>
 </LbT>
 <LbT Nm="FB3_PT1" PtT="CT">
  <LbTO NNm="FB3_PT1"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- B_0_SAMPL_CLK_n -->
  <LbTI NNm="FB9_6_N"/>
 </LbT>
 <LbT Nm="FB3_PT2" PtT="CT">
  <LbTO NNm="FB3_PT2"/>
  <!-- A_0_xpla_dummy_o_1_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- B_0_SAMPL_CLK_n -->
  <LbTI NNm="FB9_6_N"/>
 </LbT>
 <LbT Nm="FB3_PT3" PtT="CT">
  <LbTO NNm="FB3_PT3"/>
  <!-- IO13_n -->
  <LbTI NNm="FB10_4_N"/>
  <!-- B_0_SAMPL_CLK_n -->
  <LbTI NNm="FB9_6_N"/>
 </LbT>
 <LbT Nm="FB3_PT4" PtT="CT">
  <LbTO NNm="FB3_PT4"/>
  <!-- IO13_n -->
  <LbTI NNm="FB10_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT5" PtT="CT">
  <LbTO NNm="FB3_PT5"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- A_0_xpla_dummy_o_1_n -->
  <LbTI NNm="FB1_9_N"/>
 </LbT>
 <LbT Nm="FB3_PT6" PtT="CT">
  <LbTO NNm="FB3_PT6"/>
  <!-- B_0_SAMPL_CLK_n -->
  <LbTI NNm="FB9_6_N"/>
 </LbT>
 <LbT Nm="FB3_PT7" PtT="UCT">
  <LbTO NNm="FB3_PT7"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- A_0_xpla_dummy_o_1_n -->
  <LbTI NNm="FB1_9_N"/>
 </LbT>
 <LbT Nm="FB3_PT8" PtT="0">
  <LbTO NNm="FB3_PT8"/>
  <!-- SP_WEn_p -->
  <LbTI NNm="FB1_5_P"/>
  <!-- N_PZ_5586_n -->
  <LbTI NNm="FB6_15_N"/>
 </LbT>
 <LbT Nm="FB3_PT9" PtT="CLK">
  <LbTO NNm="FB3_PT9"/>
  <!-- SP_CS0n_p -->
  <LbTI NNm="FB2_1_P"/>
  <!-- SP_A19_p -->
  <LbTI NNm="FB1_2_P"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
 </LbT>
 <LbT Nm="FB3_PT10" PtT="0">
  <LbTO NNm="FB3_PT10"/>
  <!-- SP_WEn_p -->
  <LbTI NNm="FB1_5_P"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
 </LbT>
 <LbT Nm="FB3_PT11" PtT="CLK">
  <LbTO NNm="FB3_PT11"/>
  <!-- SP_CS0n_p -->
  <LbTI NNm="FB2_1_P"/>
  <!-- SP_CS1n_p -->
  <LbTI NNm="FB1_13_P"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
 </LbT>
 <LbT Nm="FB3_PT14" PtT="0">
  <LbTO NNm="FB3_PT14"/>
  <!-- B_0_ACQ_BEGIN_n -->
  <LbTI NNm="FB3_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT16" PtT="0">
  <LbTO NNm="FB3_PT16"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- B_0_ACQ_BEGIN_n -->
  <LbTI NNm="FB3_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT18" PtT="0">
  <LbTO NNm="FB3_PT18"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- INPUT_HILO_n -->
  <LbTI NNm="FB3_5_N"/>
  <!-- RAM_A0_n -->
  <LbTI NNm="FB3_14_N"/>
  <!-- RAM_A1_n -->
  <LbTI NNm="FB3_15_N"/>
  <!-- RAM_A2_n -->
  <LbTI NNm="FB1_16_N"/>
  <!-- RAM_A3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- RAM_A4_n -->
  <LbTI NNm="FB1_13_N"/>
  <!-- RAM_A5_n -->
  <LbTI NNm="FB1_12_N"/>
  <!-- RAM_A6_n -->
  <LbTI NNm="FB1_5_N"/>
  <!-- RAM_A7_n -->
  <LbTI NNm="FB1_4_N"/>
  <!-- RAM_A8_n -->
  <LbTI NNm="FB1_2_N"/>
  <!-- RAM_A9_n -->
  <LbTI NNm="FB1_1_N"/>
  <!-- RAM_A10_n -->
  <LbTI NNm="FB3_8_N"/>
  <!-- RAM_A11_n -->
  <LbTI NNm="FB3_7_N"/>
  <!-- B_0_ACQ_BEGIN_n -->
  <LbTI NNm="FB3_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT20" PtT="0">
  <LbTO NNm="FB3_PT20"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- INPUT_HILO_n -->
  <LbTI NNm="FB3_5_N"/>
  <!-- RAM_A0_n -->
  <LbTI NNm="FB3_14_N"/>
  <!-- RAM_A1_n -->
  <LbTI NNm="FB3_15_N"/>
  <!-- RAM_A2_n -->
  <LbTI NNm="FB1_16_N"/>
  <!-- RAM_A3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- RAM_A4_n -->
  <LbTI NNm="FB1_13_N"/>
  <!-- RAM_A5_n -->
  <LbTI NNm="FB1_12_N"/>
  <!-- RAM_A6_n -->
  <LbTI NNm="FB1_5_N"/>
  <!-- RAM_A7_n -->
  <LbTI NNm="FB1_4_N"/>
  <!-- RAM_A8_n -->
  <LbTI NNm="FB1_2_N"/>
  <!-- RAM_A9_n -->
  <LbTI NNm="FB1_1_N"/>
  <!-- RAM_A10_n -->
  <LbTI NNm="FB3_8_N"/>
  <!-- B_0_ACQ_BEGIN_n -->
  <LbTI NNm="FB3_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT22" PtT="0">
  <LbTO NNm="FB3_PT22"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- INPUT_HILO_n -->
  <LbTI NNm="FB3_5_N"/>
  <!-- RAM_A0_n -->
  <LbTI NNm="FB3_14_N"/>
  <!-- RAM_A1_n -->
  <LbTI NNm="FB3_15_N"/>
  <!-- RAM_A2_n -->
  <LbTI NNm="FB1_16_N"/>
  <!-- RAM_A3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- RAM_A4_n -->
  <LbTI NNm="FB1_13_N"/>
  <!-- RAM_A5_n -->
  <LbTI NNm="FB1_12_N"/>
  <!-- RAM_A6_n -->
  <LbTI NNm="FB1_5_N"/>
  <!-- RAM_A7_n -->
  <LbTI NNm="FB1_4_N"/>
  <!-- RAM_A8_n -->
  <LbTI NNm="FB1_2_N"/>
  <!-- RAM_A9_n -->
  <LbTI NNm="FB1_1_N"/>
  <!-- B_0_ACQ_BEGIN_n -->
  <LbTI NNm="FB3_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT24" PtT="0">
  <LbTO NNm="FB3_PT24"/>
  <!-- RAM_A8_n -->
  <LbTI NNm="FB1_2_N"/>
 </LbT>
 <LbT Nm="FB3_PT26" PtT="0">
  <LbTO NNm="FB3_PT26"/>
  <!-- RAM_A7_n -->
  <LbTI NNm="FB1_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT28" PtT="0">
  <LbTO NNm="FB3_PT28"/>
  <!-- RAM_A6_n -->
  <LbTI NNm="FB1_5_N"/>
 </LbT>
 <LbT Nm="FB3_PT30" PtT="0">
  <LbTO NNm="FB3_PT30"/>
  <!-- INPUT_HILO_n -->
  <LbTI NNm="FB3_5_N"/>
 </LbT>
 <LbT Nm="FB3_PT32" PtT="0">
  <LbTO NNm="FB3_PT32"/>
  <!-- RAM_A9_n -->
  <LbTI NNm="FB1_1_N"/>
 </LbT>
 <LbT Nm="FB3_PT34" PtT="0">
  <LbTO NNm="FB3_PT34"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- INPUT_HILO_n -->
  <LbTI NNm="FB3_5_N"/>
  <!-- B_0_ACQ_BEGIN_n -->
  <LbTI NNm="FB3_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT36" PtT="0">
  <LbTO NNm="FB3_PT36"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- INPUT_HILO_n -->
  <LbTI NNm="FB3_5_N"/>
  <!-- RAM_A0_n -->
  <LbTI NNm="FB3_14_N"/>
  <!-- B_0_ACQ_BEGIN_n -->
  <LbTI NNm="FB3_4_N"/>
 </LbT>
 <LbT Nm="FB3_PT38" PtT="0">
  <LbTO NNm="FB3_PT38"/>
  <!-- IO14_n -->
  <LbTI NNm="FB10_5_N"/>
  <!-- INPUT_HILO_n -->
  <LbTI NNm="FB3_5_N"/>
  <!-- RAM_A0_n -->
  <LbTI NNm="FB3_14_N"/>
  <!-- RAM_A1_n -->
  <LbTI NNm="FB3_15_N"/>
  <!-- RAM_A2_n -->
  <LbTI NNm="FB1_16_N"/>
  <!-- RAM_A3_n -->
  <LbTI NNm="FB1_14_N"/>