analyzer.blx

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

.names SP_WEn BANK2.CLK
1 1
.names SP_WEn BANK3.CLK
1 1
.names SP_WEn BANK4.CLK
1 1
.names IO13.Q D_0_TRIGADR_RD0.CLK
1 1
.names RAM_A0.Q D_0_TRIGADR_RD0.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD0.AR
10 1
.names IO13.Q D_0_TRIGADR_RD1.CLK
1 1
.names RAM_A1.Q D_0_TRIGADR_RD1.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD1.AR
10 1
.names IO13.Q D_0_TRIGADR_RD2.CLK
1 1
.names RAM_A2.Q D_0_TRIGADR_RD2.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD2.AR
10 1
.names IO13.Q D_0_TRIGADR_RD3.CLK
1 1
.names RAM_A3.Q D_0_TRIGADR_RD3.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD3.AR
10 1
.names IO13.Q D_0_TRIGADR_RD4.CLK
1 1
.names RAM_A4.Q D_0_TRIGADR_RD4.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD4.AR
10 1
.names IO13.Q D_0_TRIGADR_RD5.CLK
1 1
.names RAM_A5.Q D_0_TRIGADR_RD5.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD5.AR
10 1
.names IO13.Q D_0_TRIGADR_RD6.CLK
1 1
.names RAM_A6.Q D_0_TRIGADR_RD6.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD6.AR
10 1
.names IO13.Q D_0_TRIGADR_RD7.CLK
1 1
.names RAM_A7.Q D_0_TRIGADR_RD7.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD7.AR
10 1
.names IO13.Q D_0_TRIGADR_RD8.CLK
1 1
.names RAM_A8.Q D_0_TRIGADR_RD8.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD8.AR
10 1
.names IO13.Q D_0_TRIGADR_RD9.CLK
1 1
.names RAM_A9.Q D_0_TRIGADR_RD9.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD9.AR
10 1
.names IO13.Q D_0_TRIGADR_RD10.CLK
1 1
.names RAM_A10.Q D_0_TRIGADR_RD10.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD10.AR
10 1
.names IO13.Q D_0_TRIGADR_RD11.CLK
1 1
.names RAM_A11.Q D_0_TRIGADR_RD11.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD11.AR
10 1
.names IO13.Q D_0_TRIGADR_RD12.CLK
1 1
.names RAM_A12.Q D_0_TRIGADR_RD12.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIGADR_RD12.AR
10 1
.names IO13.Q D_0_TRIG_HILO.CLK
1 1
.names INPUT_HILO.Q D_0_TRIG_HILO.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q D_0_TRIG_HILO.AR
10 1
.names SP_WEn E_0_xpla_dummy_o_64.CLK
1 1
.names SP_WEn E_0_xpla_dummy_o_66.CLK
1 1
.names SP_WEn E_0_xpla_dummy_o_68.CLK
1 1
.names B_0_SAMPL_CLK INPUT_HILO.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q INPUT_HILO.AR
10 1
.names B_0_N177842 IO13.CLK-
1 1
.names IO14.Q IO13.AR
0 1
.names SP_OEn IN_STATUS0.CLK
0 1
.names CH_IN0 IN_STATUS0.D
1 1
.names SP_OEn IN_STATUS1.CLK
0 1
.names CH_IN1 IN_STATUS1.D
1 1
.names SP_OEn IN_STATUS2.CLK
0 1
.names CH_IN2 IN_STATUS2.D
1 1
.names SP_OEn IN_STATUS3.CLK
0 1
.names CH_IN3 IN_STATUS3.D
1 1
.names SP_OEn IN_STATUS4.CLK
0 1
.names CH_IN4 IN_STATUS4.D
1 1
.names SP_OEn IN_STATUS5.CLK
0 1
.names CH_IN5 IN_STATUS5.D
1 1
.names SP_OEn IN_STATUS6.CLK
0 1
.names CH_IN6 IN_STATUS6.D
1 1
.names SP_OEn IN_STATUS7.CLK
0 1
.names CH_IN7 IN_STATUS7.D
1 1
.names N_PZ_5597 RAM_D0.CLK-
1 1
.names N_PZ_5597 RAM_D1.CLK-
1 1
.names N_PZ_5597 RAM_D2.CLK-
1 1
.names N_PZ_5597 RAM_D3.CLK-
1 1
.names N_PZ_5597 RAM_D4.CLK-
1 1
.names N_PZ_5597 RAM_D5.CLK-
1 1
.names N_PZ_5597 RAM_D6.CLK-
1 1
.names N_PZ_5597 RAM_D7.CLK-
1 1
.names N_PZ_5597 RAM_D8.CLK-
1 1
.names CH_IN0 RAM_D8.D
1 1
.names N_PZ_5597 RAM_D9.CLK-
1 1
.names CH_IN1 RAM_D9.D
1 1
.names N_PZ_5597 RAM_D10.CLK-
1 1
.names CH_IN2 RAM_D10.D
1 1
.names N_PZ_5597 RAM_D11.CLK-
1 1
.names CH_IN3 RAM_D11.D
1 1
.names N_PZ_5597 RAM_D12.CLK-
1 1
.names CH_IN4 RAM_D12.D
1 1
.names N_PZ_5597 RAM_D13.CLK-
1 1
.names CH_IN5 RAM_D13.D
1 1
.names N_PZ_5597 RAM_D14.CLK-
1 1
.names CH_IN6 RAM_D14.D
1 1
.names N_PZ_5597 RAM_D15.CLK-
1 1
.names CH_IN7 RAM_D15.D
1 1
.names B_0_SAMPL_CLK RAM_A0.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A0.AR
10 1
.names B_0_SAMPL_CLK RAM_A1.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A1.AR
10 1
.names B_0_SAMPL_CLK RAM_A2.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A2.AR
10 1
.names B_0_SAMPL_CLK RAM_A3.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A3.AR
10 1
.names B_0_SAMPL_CLK RAM_A4.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A4.AR
10 1
.names B_0_SAMPL_CLK RAM_A5.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A5.AR
10 1
.names B_0_SAMPL_CLK RAM_A6.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A6.AR
10 1
.names B_0_SAMPL_CLK RAM_A7.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A7.AR
10 1
.names B_0_SAMPL_CLK RAM_A8.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A8.AR
10 1
.names B_0_SAMPL_CLK RAM_A9.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A9.AR
10 1
.names B_0_SAMPL_CLK RAM_A10.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A10.AR
10 1
.names B_0_SAMPL_CLK RAM_A11.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A11.AR
10 1
.names B_0_SAMPL_CLK RAM_A12.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q RAM_A12.AR
10 1
.names TRIGGER0.Q TRIGGER1.Q TRIGGER2.Q TRIGGER3.Q TRIGGER4.Q TRIGGER5.Q 
       TRIGGER6.Q TRIGGER7.Q TRIGGER8.Q TRIGGER9.Q TRIGGER10.Q TRIGGER11.Q 
       TRIGGER12.Q TRIGGER13.Q TRIGGER14.Q TRIGGER15.Q RAM_D8.Q RAM_D9.Q 
       RAM_D10.Q RAM_D11.Q RAM_D12.Q RAM_D13.Q RAM_D14.Q RAM_D15.Q B_0_N177842
00--------------1------- 1
11--------------0------- 1
--00-------------1------ 1
--11-------------0------ 1
----00------------1----- 1
----11------------0----- 1
------00-----------1---- 1
------11-----------0---- 1
--------00----------1--- 1
--------11----------0--- 1
----------00---------1-- 1
----------11---------0-- 1
------------00--------1- 1
------------11--------0- 1
--------------00-------1 1
--------------11-------0 1
.names SELCLK2.Q C_0_DWN_OUT.Q C_0_DWN_CLK B_0_SAMPL_CLK
11- 1
0-1 1
.names SELCLK1.Q SELCLK0.Q SYS_CLK C_0_SYS_CLK2.Q C_0_SYS_CLK4.Q C_0_DWN_CLK
001-- 1
01-1- 1
10--1 1
.names N_PZ_5599 B_0_N133030.CLK
1 1
.names N_PZ_5599 B_0_N133028.CLK
1 1
.names N_PZ_5599 B_0_N133026.CLK
1 1
.names N_PZ_5599 B_0_N133024.CLK
1 1
.names N_PZ_5599 B_0_N133022.CLK
1 1
.names N_PZ_5599 B_0_N133020.CLK
1 1
.names N_PZ_5599 B_0_N133018.CLK
1 1
.names N_PZ_5599 B_0_N133062.CLK
1 1
.names N_PZ_5599 B_0_N133060.CLK
1 1
.names N_PZ_5599 B_0_N133058.CLK
1 1
.names N_PZ_5599 B_0_N139394.CLK
1 1
.names N_PZ_5599 B_0_N139401.CLK
1 1
.names N_PZ_5599 B_0_xpla_dummy_o_7.CLK
1 1
.names N_PZ_5599 B_0_xpla_dummy_o_8.CLK
1 1
.names N_PZ_5599 B_0_xpla_dummy_o_9.CLK
1 1
.names N_PZ_5599 B_0_xpla_dummy_o_10.CLK
1 1
.names B_0_SAMPL_CLK B_0_xpla_dummy_o_11.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q B_0_xpla_dummy_o_11.AR
10 1
.names IO14.Q A_0_xpla_dummy_o_1.Q B_0_ACQ_BEGIN.CLK
10 1
.names B_0_SAMPL_CLK B_0_ACQ_BEGIN.AR
1 1
.names SYS_CLK A_0_QA.CLK
1 1
.names IO14.Q A_0_QA.AR
0 1
.names SYS_CLK A_0_xpla_dummy_o_1.CLK
1 1
.names A_0_QA.Q A_0_xpla_dummy_o_1.D
1 1
.names IO14.Q A_0_xpla_dummy_o_1.AR
0 1
.names SYS_CLK C_0_DWN_OUT.CLK
1 1
.names C_0_SYS_CLK2.Q C_0_SYS_CLK4.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_SYS_CLK4.AR
10 1
.names SYS_CLK C_0_SYS_CLK2.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_SYS_CLK2.AR
10 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133030.AR
10 1
.names C_0_DWN_CLK C_0_N133030.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133028.AR
10 1
.names C_0_DWN_CLK C_0_N133028.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133026.AR
10 1
.names C_0_DWN_CLK C_0_N133026.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133024.AR
10 1
.names C_0_DWN_CLK C_0_N133024.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133022.AR
10 1
.names C_0_DWN_CLK C_0_N133022.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133020.AR
10 1
.names C_0_DWN_CLK C_0_N133020.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133018.AR
10 1
.names C_0_DWN_CLK C_0_N133018.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133062.AR
10 1
.names C_0_DWN_CLK C_0_N133062.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133060.AR
10 1
.names C_0_DWN_CLK C_0_N133060.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133058.AR
10 1
.names C_0_DWN_CLK C_0_N133058.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133056.AR
10 1
.names C_0_DWN_CLK C_0_N133056.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133054.AR
10 1
.names C_0_DWN_CLK C_0_N133054.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133052.AR
10 1
.names C_0_DWN_CLK C_0_N133052.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133234.AR
10 1
.names C_0_DWN_CLK C_0_N133234.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_N133197.AR
10 1
.names C_0_DWN_CLK C_0_N133197.CLK
1 1
.names IO14.Q A_0_xpla_dummy_o_1.Q C_0_xpla_dummy_o_3.AR
10 1
.names C_0_DWN_CLK C_0_xpla_dummy_o_3.CLK
1 1
.names N_PZ_5596 SP_D0.OE
1 1
.names N_PZ_5596 SP_D1.OE
1 1
.names N_PZ_5596 SP_D2.OE
1 1
.names N_PZ_5596 SP_D3.OE
1 1
.names N_PZ_5596 SP_D4.OE
1 1
.names N_PZ_5596 SP_D5.OE
1 1
.names N_PZ_5596 SP_D6.OE
1 1
.names N_PZ_5596 SP_D7.OE
1 1
.names N_PZ_5596 SP_D8.OE
1 1
.names N_PZ_5596 SP_D9.OE
1 1
.names N_PZ_5596 SP_D10.OE
1 1
.names N_PZ_5596 SP_D11.OE
1 1
.names N_PZ_5596 SP_D12.OE
1 1
.names N_PZ_5596 SP_D13.OE
1 1
.names N_PZ_5596 SP_D14.OE
1 1
.names N_PZ_5596 SP_D15.OE
1 1
.names N_PZ_5595 D0.OE-
1 1
.names N_PZ_5595 D1.OE-
1 1
.names N_PZ_5595 D2.OE-
1 1
.names N_PZ_5595 D3.OE-
1 1
.names N_PZ_5595 D4.OE-
1 1
.names N_PZ_5595 D5.OE-
1 1
.names N_PZ_5595 D6.OE-
1 1
.names N_PZ_5595 D7.OE-
1 1