📄 analyzer.blx
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# XPLAOPT Version 3.43
# XPLAOPT -dev xcr3256xl-10cs280 -mode 1 -th 18 -fi 26 -xor n -reg -ucf
# c:\dad'sstuff\visor\logicanalyzer\analyzer\analyzer.ucf -it blif -i analyzer.bl3 -ot blif -o analyzer.blx -run s -log
# analyzer.er2 -ctrl analyzer.ctrl
#$ MODULE LogicAnalyzer
#$ PINS 9 A0:T5 A1:W10 A10:V5 A11:W5 A12:W4 A13:W3 A14:U6 A15:T6 A16:R6
#$ PINS 10 A17:W7 A18:G1 A19:U5 A2:T9 A20:U4 A3:U9 A4:T8 A5:V7 A6:U7 A7:T7
#$ PINS 7 A8:V6 A9:W6 CH_IN0:B1 CH_IN1:C3 CH_IN2:A4 CH_IN3:B5 CH_IN4:C5
#$ PINS 8 CH_IN5:A5 CH_IN6:E6 CH_IN7:D6 D0:A14 D1:B13 D10:B12 D11:D10 D12:C9
#$ PINS 10 D13:B8 D14:C7 D15:B7 D2:D12 D3:A12 D4:C10 D5:C8 D6:D7 D7:A7 D8:C13
#$ PINS 6 D9:A13 FLASH_CS0n:E14 FLASH_W_PROTECTn:H2 IO13:E2 IO14:E4 IO15:E1
#$ PINS 7 LED_0:F5 LED_1:F3 LED_2:F4 LED_3:G3 OEn:D14 RESET_MEMn:T13 RWn:J2
#$ PINS 6 SP_A1:T17 SP_A10:F17 SP_A11:H17 SP_A12:M18 SP_A13:L17 SP_A14:E18
#$ PINS 6 SP_A15:K18 SP_A16:H19 SP_A17:L16 SP_A18:M17 SP_A19:E19 SP_A2:R16
#$ PINS 6 SP_A20:F19 SP_A21:H18 SP_A3:R17 SP_A4:N16 SP_A5:M16 SP_A6:R19
#$ PINS 6 SP_A7:N18 SP_A8:K17 SP_A9:J17 SP_CS0n:B19 SP_CS1n:G16 SP_D0:V16
#$ PINS 6 SP_D1:W15 SP_D10:U15 SP_D11:C16 SP_D12:A16 SP_D13:B17 SP_D14:B18
#$ PINS 6 SP_D15:F15 SP_D2:T15 SP_D3:D15 SP_D4:E15 SP_D5:A15 SP_D6:A17
#$ PINS 6 SP_D7:A18 SP_D8:V15 SP_D9:T16 SP_IRQn:G19 SP_OEn:G17 SP_RESETn:N17
#$ PINS 4 SP_WEn:F18 SRAM_CS1n:K2 SRAM_LOW_BYTEn:K3 SRAM_UPPER_BYTEn:J3
#$ PINS 1 SYS_CLK:A10
#$ NODES 5 A_0_QA A_0_xpla_dummy_o_1 B_0_ACQ_BEGIN B_0_N133018 B_0_N133020
#$ NODES 5 B_0_N133022 B_0_N133024 B_0_N133026 B_0_N133028 B_0_N133030
#$ NODES 5 B_0_N133058 B_0_N133060 B_0_N133062 B_0_N139394 B_0_N139401
#$ NODES 3 B_0_N177842'co' B_0_SAMPL_CLK'co' B_0_xpla_dummy_o_10
#$ NODES 3 B_0_xpla_dummy_o_11 B_0_xpla_dummy_o_7 B_0_xpla_dummy_o_8
#$ NODES 5 B_0_xpla_dummy_o_9 BANK0'co' BANK1'co' BANK2'co' BANK3'co'
#$ NODES 5 BANK4'co' C_0_DWN_CLK'co' C_0_DWN_OUT C_0_N133018 C_0_N133020
#$ NODES 5 C_0_N133022 C_0_N133024 C_0_N133026 C_0_N133028 C_0_N133030
#$ NODES 5 C_0_N133052 C_0_N133054 C_0_N133056 C_0_N133058 C_0_N133060
#$ NODES 5 C_0_N133062 C_0_N133197 C_0_N133234 C_0_SYS_CLK2 C_0_SYS_CLK4
#$ NODES 4 C_0_xpla_dummy_o_3 CNT_DWN0'co' CNT_DWN1'co' CNT_DWN10'co'
#$ NODES 5 CNT_DWN11'co' CNT_DWN12'co' CNT_DWN2'co' CNT_DWN3'co' CNT_DWN4'co'
#$ NODES 5 CNT_DWN5'co' CNT_DWN6'co' CNT_DWN7'co' CNT_DWN8'co' CNT_DWN9'co'
#$ NODES 4 D_0_TRIG_HILO D_0_TRIGADR_RD0 D_0_TRIGADR_RD1 D_0_TRIGADR_RD10
#$ NODES 4 D_0_TRIGADR_RD11 D_0_TRIGADR_RD12 D_0_TRIGADR_RD2 D_0_TRIGADR_RD3
#$ NODES 4 D_0_TRIGADR_RD4 D_0_TRIGADR_RD5 D_0_TRIGADR_RD6 D_0_TRIGADR_RD7
#$ NODES 3 D_0_TRIGADR_RD8 D_0_TRIGADR_RD9 E_0_xpla_dummy_o_64
#$ NODES 3 E_0_xpla_dummy_o_66 E_0_xpla_dummy_o_68 IN_STATUS0'co'
#$ NODES 4 IN_STATUS1'co' IN_STATUS2'co' IN_STATUS3'co' IN_STATUS4'co'
#$ NODES 4 IN_STATUS5'co' IN_STATUS6'co' IN_STATUS7'co' INPUT_HILO'co'
#$ NODES 4 N_PZ_5586'ke' N_PZ_5587'ke' N_PZ_5595'co' N_PZ_5596'co'
#$ NODES 5 N_PZ_5597'co' N_PZ_5599'co' RAM_A0'co' RAM_A1'co' RAM_A10'co'
#$ NODES 5 RAM_A11'co' RAM_A12'co' RAM_A2'co' RAM_A3'co' RAM_A4'co'
#$ NODES 6 RAM_A5'co' RAM_A6'co' RAM_A7'co' RAM_A8'co' RAM_A9'co' RAM_D0'co'
#$ NODES 5 RAM_D1'co' RAM_D10'co' RAM_D11'co' RAM_D12'co' RAM_D13'co'
#$ NODES 5 RAM_D14'co' RAM_D15'co' RAM_D2'co' RAM_D3'co' RAM_D4'co'
#$ NODES 6 RAM_D5'co' RAM_D6'co' RAM_D7'co' RAM_D8'co' RAM_D9'co' SELCLK0'co'
#$ NODES 5 SELCLK1'co' SELCLK2'co' TRIGGER0'co' TRIGGER1'co' TRIGGER10'co'
#$ NODES 4 TRIGGER11'co' TRIGGER12'co' TRIGGER13'co' TRIGGER14'co'
#$ NODES 5 TRIGGER15'co' TRIGGER2'co' TRIGGER3'co' TRIGGER4'co' TRIGGER5'co'
#$ NODES 4 TRIGGER6'co' TRIGGER7'co' TRIGGER8'co' TRIGGER9'co'
.model LOGICANALYZER
.inputs SP_A21 SP_A10 SP_A4 SP_CS0n SP_A11 SP_A5 SP_A12 SP_A6 SP_A13 SP_A7
SP_A14 SP_A8 CH_IN0 SP_A15 SP_A9 CH_IN1 SP_A16 SYS_CLK CH_IN2 SP_A17
SP_OEn CH_IN3 SP_A18 CH_IN4 SP_A19 CH_IN5 CH_IN6 CH_IN7 SP_RESETn
SP_A1 SP_A2 SP_WEn SP_A20 SP_A3 SP_CS1n TRIGGER0.Q TRIGGER1.Q
TRIGGER2.Q TRIGGER3.Q TRIGGER4.Q TRIGGER5.Q TRIGGER6.Q TRIGGER7.Q
TRIGGER8.Q TRIGGER9.Q TRIGGER10.Q TRIGGER11.Q TRIGGER12.Q TRIGGER13.Q
TRIGGER14.Q TRIGGER15.Q CNT_DWN0.Q CNT_DWN1.Q CNT_DWN2.Q CNT_DWN3.Q
CNT_DWN4.Q CNT_DWN5.Q CNT_DWN6.Q CNT_DWN7.Q CNT_DWN8.Q CNT_DWN9.Q
CNT_DWN10.Q CNT_DWN11.Q CNT_DWN12.Q SELCLK0.Q SELCLK1.Q SELCLK2.Q
IO14.Q BANK0.Q BANK1.Q BANK2.Q BANK3.Q BANK4.Q D_0_TRIGADR_RD0.Q
D_0_TRIGADR_RD1.Q D_0_TRIGADR_RD2.Q D_0_TRIGADR_RD3.Q
D_0_TRIGADR_RD4.Q D_0_TRIGADR_RD5.Q D_0_TRIGADR_RD6.Q
D_0_TRIGADR_RD7.Q D_0_TRIGADR_RD8.Q D_0_TRIGADR_RD9.Q
D_0_TRIGADR_RD10.Q D_0_TRIGADR_RD11.Q D_0_TRIGADR_RD12.Q
D_0_TRIG_HILO.Q E_0_xpla_dummy_o_64.Q E_0_xpla_dummy_o_66.Q
E_0_xpla_dummy_o_68.Q INPUT_HILO.Q IO13.Q IN_STATUS0.Q IN_STATUS1.Q
IN_STATUS2.Q IN_STATUS3.Q IN_STATUS4.Q IN_STATUS5.Q IN_STATUS6.Q
IN_STATUS7.Q RAM_D0.Q RAM_D1.Q RAM_D2.Q RAM_D3.Q RAM_D4.Q RAM_D5.Q
RAM_D6.Q RAM_D7.Q RAM_D8.Q RAM_D9.Q RAM_D10.Q RAM_D11.Q RAM_D12.Q
RAM_D13.Q RAM_D14.Q RAM_D15.Q RAM_A0.Q RAM_A1.Q RAM_A2.Q RAM_A3.Q
RAM_A4.Q RAM_A5.Q RAM_A6.Q RAM_A7.Q RAM_A8.Q RAM_A9.Q RAM_A10.Q
RAM_A11.Q RAM_A12.Q B_0_N133030.Q B_0_N133028.Q B_0_N133026.Q
B_0_N133024.Q B_0_N133022.Q B_0_N133020.Q B_0_N133018.Q B_0_N133062.Q
B_0_N133060.Q B_0_N133058.Q B_0_N139394.Q B_0_N139401.Q
B_0_xpla_dummy_o_7.Q B_0_xpla_dummy_o_8.Q B_0_xpla_dummy_o_9.Q
B_0_xpla_dummy_o_10.Q B_0_ACQ_BEGIN.Q A_0_QA.Q A_0_xpla_dummy_o_1.Q
C_0_SYS_CLK4.Q C_0_SYS_CLK2.Q C_0_DWN_OUT.Q C_0_N133030.Q
C_0_N133028.Q C_0_N133026.Q C_0_N133024.Q C_0_N133022.Q C_0_N133020.Q
C_0_N133018.Q C_0_N133062.Q C_0_N133060.Q C_0_N133058.Q C_0_N133056.Q
C_0_N133054.Q C_0_N133052.Q C_0_N133234.Q C_0_N133197.Q
C_0_xpla_dummy_o_3.Q D11.PIN D3.PIN SP_D7.PIN D12.PIN D4.PIN
SP_D8.PIN D13.PIN D5.PIN SP_D9.PIN D14.PIN D6.PIN SP_D10.PIN D15.PIN
D7.PIN SP_D11.PIN D8.PIN SP_D12.PIN D9.PIN SP_D13.PIN SP_D14.PIN
SP_D15.PIN SP_D0.PIN SP_D1.PIN SP_D2.PIN SP_D3.PIN D0.PIN SP_D4.PIN
D1.PIN SP_D5.PIN D10.PIN D2.PIN SP_D6.PIN
.outputs D11 D3 SP_D7 A14 A0 D12 D4 SP_D8 A15 A1 D13 D5 SP_D9 A16 A2 D14 D6
SP_D10 OEn A17 A3 D15 D7 SP_D11 A18 A4 D8 SP_D12 RWn A19 A5
SRAM_LOW_BYTEn D9 SP_D13 A6 SRAM_UPPER_BYTEn SP_D14 A7 SP_D15 A8 A9
SP_D0 IO15 SP_D1 SP_IRQn LED_0 SP_D2 A20 LED_1 SP_D3 FLASH_CS0n A10
LED_2 RESET_MEMn D0 SP_D4 SRAM_CS1n A11 LED_3 D1 SP_D5 A12
FLASH_W_PROTECTn D10 D2 SP_D6 A13 TRIGGER0.CLK TRIGGER1.CLK
TRIGGER2.CLK TRIGGER3.CLK TRIGGER4.CLK TRIGGER5.CLK TRIGGER6.CLK
TRIGGER7.CLK TRIGGER8.CLK TRIGGER9.CLK TRIGGER10.CLK TRIGGER11.CLK
TRIGGER12.CLK TRIGGER13.CLK TRIGGER14.CLK TRIGGER15.CLK CNT_DWN0.CLK
CNT_DWN1.CLK CNT_DWN2.CLK CNT_DWN3.CLK CNT_DWN4.CLK CNT_DWN5.CLK
CNT_DWN6.CLK CNT_DWN7.CLK CNT_DWN8.CLK CNT_DWN9.CLK CNT_DWN10.CLK
CNT_DWN11.CLK CNT_DWN12.CLK SELCLK0.CLK SELCLK1.CLK SELCLK2.CLK
IO14.CLK IO14.AR BANK0.CLK BANK1.CLK BANK2.CLK BANK3.CLK BANK4.CLK
D_0_TRIGADR_RD0.CLK D_0_TRIGADR_RD0.D D_0_TRIGADR_RD0.AR
D_0_TRIGADR_RD1.CLK D_0_TRIGADR_RD1.D D_0_TRIGADR_RD1.AR
D_0_TRIGADR_RD2.CLK D_0_TRIGADR_RD2.D D_0_TRIGADR_RD2.AR
D_0_TRIGADR_RD3.CLK D_0_TRIGADR_RD3.D D_0_TRIGADR_RD3.AR
D_0_TRIGADR_RD4.CLK D_0_TRIGADR_RD4.D D_0_TRIGADR_RD4.AR
D_0_TRIGADR_RD5.CLK D_0_TRIGADR_RD5.D D_0_TRIGADR_RD5.AR
D_0_TRIGADR_RD6.CLK D_0_TRIGADR_RD6.D D_0_TRIGADR_RD6.AR
D_0_TRIGADR_RD7.CLK D_0_TRIGADR_RD7.D D_0_TRIGADR_RD7.AR
D_0_TRIGADR_RD8.CLK D_0_TRIGADR_RD8.D D_0_TRIGADR_RD8.AR
D_0_TRIGADR_RD9.CLK D_0_TRIGADR_RD9.D D_0_TRIGADR_RD9.AR
D_0_TRIGADR_RD10.CLK D_0_TRIGADR_RD10.D D_0_TRIGADR_RD10.AR
D_0_TRIGADR_RD11.CLK D_0_TRIGADR_RD11.D D_0_TRIGADR_RD11.AR
D_0_TRIGADR_RD12.CLK D_0_TRIGADR_RD12.D D_0_TRIGADR_RD12.AR
D_0_TRIG_HILO.CLK D_0_TRIG_HILO.D D_0_TRIG_HILO.AR
E_0_xpla_dummy_o_64.CLK E_0_xpla_dummy_o_66.CLK
E_0_xpla_dummy_o_68.CLK INPUT_HILO.CLK INPUT_HILO.AR IO13.CLK IO13.AR
IN_STATUS0.CLK IN_STATUS0.D IN_STATUS1.CLK IN_STATUS1.D
IN_STATUS2.CLK IN_STATUS2.D IN_STATUS3.CLK IN_STATUS3.D
IN_STATUS4.CLK IN_STATUS4.D IN_STATUS5.CLK IN_STATUS5.D
IN_STATUS6.CLK IN_STATUS6.D IN_STATUS7.CLK IN_STATUS7.D RAM_D0.CLK
RAM_D1.CLK RAM_D2.CLK RAM_D3.CLK RAM_D4.CLK RAM_D5.CLK RAM_D6.CLK
RAM_D7.CLK RAM_D8.CLK RAM_D8.D RAM_D9.CLK RAM_D9.D RAM_D10.CLK
RAM_D10.D RAM_D11.CLK RAM_D11.D RAM_D12.CLK RAM_D12.D RAM_D13.CLK
RAM_D13.D RAM_D14.CLK RAM_D14.D RAM_D15.CLK RAM_D15.D RAM_A0.CLK
RAM_A0.AR RAM_A1.CLK RAM_A1.AR RAM_A2.CLK RAM_A2.AR RAM_A3.CLK
RAM_A3.AR RAM_A4.CLK RAM_A4.AR RAM_A5.CLK RAM_A5.AR RAM_A6.CLK
RAM_A6.AR RAM_A7.CLK RAM_A7.AR RAM_A8.CLK RAM_A8.AR RAM_A9.CLK
RAM_A9.AR RAM_A10.CLK RAM_A10.AR RAM_A11.CLK RAM_A11.AR RAM_A12.CLK
RAM_A12.AR B_0_N133030.CLK B_0_N133028.CLK B_0_N133026.CLK
B_0_N133024.CLK B_0_N133022.CLK B_0_N133020.CLK B_0_N133018.CLK
B_0_N133062.CLK B_0_N133060.CLK B_0_N133058.CLK B_0_N139394.CLK
B_0_N139401.CLK B_0_xpla_dummy_o_7.CLK B_0_xpla_dummy_o_8.CLK
B_0_xpla_dummy_o_9.CLK B_0_xpla_dummy_o_10.CLK
B_0_xpla_dummy_o_11.CLK B_0_xpla_dummy_o_11.AR B_0_ACQ_BEGIN.CLK
B_0_ACQ_BEGIN.AR A_0_QA.CLK A_0_QA.AR A_0_xpla_dummy_o_1.CLK
A_0_xpla_dummy_o_1.D A_0_xpla_dummy_o_1.AR C_0_DWN_OUT.CLK
C_0_SYS_CLK4.CLK C_0_SYS_CLK4.AR C_0_SYS_CLK2.CLK C_0_SYS_CLK2.AR
C_0_N133030.AR C_0_N133030.CLK C_0_N133028.AR C_0_N133028.CLK
C_0_N133026.AR C_0_N133026.CLK C_0_N133024.AR C_0_N133024.CLK
C_0_N133022.AR C_0_N133022.CLK C_0_N133020.AR C_0_N133020.CLK
C_0_N133018.AR C_0_N133018.CLK C_0_N133062.AR C_0_N133062.CLK
C_0_N133060.AR C_0_N133060.CLK C_0_N133058.AR C_0_N133058.CLK
C_0_N133056.AR C_0_N133056.CLK C_0_N133054.AR C_0_N133054.CLK
C_0_N133052.AR C_0_N133052.CLK C_0_N133234.AR C_0_N133234.CLK
C_0_N133197.AR C_0_N133197.CLK C_0_xpla_dummy_o_3.AR
C_0_xpla_dummy_o_3.CLK SP_D0.OE SP_D1.OE SP_D2.OE SP_D3.OE SP_D4.OE
SP_D5.OE SP_D6.OE SP_D7.OE SP_D8.OE SP_D9.OE SP_D10.OE SP_D11.OE
SP_D12.OE SP_D13.OE SP_D14.OE SP_D15.OE D0.OE D1.OE D2.OE D3.OE D4.OE
D5.OE D6.OE D7.OE D8.OE D9.OE D10.OE D11.OE D12.OE D13.OE D14.OE
D15.OE TRIGGER0.T TRIGGER1.T TRIGGER2.T TRIGGER3.T TRIGGER4.T
TRIGGER5.T TRIGGER6.T TRIGGER7.T TRIGGER8.T TRIGGER9.T TRIGGER10.T
TRIGGER11.T TRIGGER12.T TRIGGER13.T TRIGGER14.T TRIGGER15.T
CNT_DWN0.T CNT_DWN1.T CNT_DWN2.T CNT_DWN3.T CNT_DWN4.T CNT_DWN5.T
CNT_DWN6.T CNT_DWN7.T CNT_DWN8.T CNT_DWN9.T CNT_DWN10.T CNT_DWN11.T
CNT_DWN12.T SELCLK0.T SELCLK1.T SELCLK2.T IO14.T BANK0.T BANK1.T
BANK2.T BANK3.T BANK4.T E_0_xpla_dummy_o_64.T E_0_xpla_dummy_o_66.T
E_0_xpla_dummy_o_68.T INPUT_HILO.T IO13.T RAM_D0.T RAM_D1.T RAM_D2.T
RAM_D3.T RAM_D4.T RAM_D5.T RAM_D6.T RAM_D7.T RAM_A0.T RAM_A1.T
RAM_A2.T RAM_A3.T RAM_A4.T RAM_A5.T RAM_A6.T RAM_A7.T RAM_A8.T
RAM_A9.T RAM_A10.T RAM_A11.T RAM_A12.T B_0_N133028.T B_0_N133026.T
B_0_N133024.T B_0_N133022.T B_0_N133020.T B_0_N133018.T B_0_N133062.T
B_0_N133060.T B_0_N133058.T B_0_N139394.T B_0_N139401.T
B_0_xpla_dummy_o_7.T B_0_xpla_dummy_o_8.T B_0_xpla_dummy_o_9.T
B_0_xpla_dummy_o_10.T B_0_xpla_dummy_o_11.T B_0_ACQ_BEGIN.T A_0_QA.T
C_0_SYS_CLK4.T C_0_SYS_CLK2.T C_0_N133030.T C_0_N133028.T
C_0_N133026.T C_0_N133024.T C_0_N133022.T C_0_N133020.T C_0_N133018.T
C_0_N133062.T C_0_N133060.T C_0_N133058.T C_0_N133056.T C_0_N133054.T
C_0_N133052.T C_0_N133234.T C_0_N133197.T C_0_xpla_dummy_o_3.T
B_0_N133030.T C_0_DWN_OUT.D
.names IO14.Q RAM_D11.Q SP_D11.PIN D11
11- 1
0-1 1
.names IO14.Q RAM_D3.Q SP_D3.PIN D3
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD7.Q IN_STATUS7.Q D7.PIN N_PZ_5587 SP_D7
---11 1
01--0 1
1-1-0 1
.names SP_A15 IO14.Q BANK1.Q A14
10- 1
-11 1
.names IO14.Q SP_A1 RAM_A0.Q A0
01- 1
1-1 1
.names IO14.Q RAM_D12.Q SP_D12.PIN D12
11- 1
0-1 1
.names IO14.Q RAM_D4.Q SP_D4.PIN D4
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD8.Q D8.PIN N_PZ_5587 SP_D8
--11 1
01-0 1
.names SP_A16 IO14.Q BANK2.Q A15
10- 1
-11 1
.names IO14.Q SP_A2 RAM_A1.Q A1
01- 1
1-1 1
.names IO14.Q RAM_D13.Q SP_D13.PIN D13
11- 1
0-1 1
.names IO14.Q RAM_D5.Q SP_D5.PIN D5
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD9.Q D9.PIN N_PZ_5587 SP_D9
--11 1
01-0 1
.names SP_A17 IO14.Q BANK3.Q A16
10- 1
-11 1
.names IO14.Q SP_A3 RAM_A2.Q A2
01- 1
1-1 1
.names IO14.Q RAM_D14.Q SP_D14.PIN D14
11- 1
0-1 1
.names IO14.Q RAM_D6.Q SP_D6.PIN D6
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD10.Q D10.PIN N_PZ_5587 SP_D10
--11 1
01-0 1
.names SP_OEn IO14.Q OEn-
00 1
.names SP_A18 IO14.Q BANK4.Q A17
10- 1
-11 1
.names IO14.Q SP_A4 RAM_A3.Q A3
01- 1
1-1 1
.names IO14.Q RAM_D15.Q SP_D15.PIN D15
11- 1
0-1 1
.names IO14.Q RAM_D7.Q SP_D7.PIN D7
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD11.Q D11.PIN N_PZ_5587 SP_D11
--11 1
01-0 1
.names SP_A19 A18
1 1
.names IO14.Q SP_A5 RAM_A4.Q A4
01- 1
1-1 1
.names IO14.Q RAM_D8.Q SP_D8.PIN D8
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD12.Q D12.PIN N_PZ_5587 SP_D12
--11 1
01-0 1
.names SP_WEn IO14.Q INPUT_HILO.Q RWn
10- 1
-11 1
.names SP_A20 A19
1 1
.names IO14.Q SP_A6 RAM_A5.Q A5
01- 1
1-1 1
.names SRAM_LOW_BYTEn
.names IO14.Q RAM_D9.Q SP_D9.PIN D9
11- 1
0-1 1
.names SP_A1 D_0_TRIG_HILO.Q D13.PIN N_PZ_5587 SP_D13
--11 1
01-0 1
.names IO14.Q SP_A7 RAM_A6.Q A6
01- 1
1-1 1
.names SRAM_UPPER_BYTEn
.names SP_A1 IO13.Q D14.PIN N_PZ_5587 SP_D14
--11 1
01-0 1
.names IO14.Q SP_A8 RAM_A7.Q A7
01- 1
1-1 1
.names SP_A1 IO14.Q D15.PIN N_PZ_5587 SP_D15
--11 1
01-0 1
.names IO14.Q SP_A9 RAM_A8.Q A8
01- 1
1-1 1
.names IO14.Q SP_A10 RAM_A9.Q A9
01- 1
1-1 1
.names SP_A1 D_0_TRIGADR_RD0.Q IN_STATUS0.Q D0.PIN N_PZ_5587 SP_D0
---11 1
01--0 1
1-1-0 1
.names SRAM_CS1n IO15
1 1
.names SP_A1 D_0_TRIGADR_RD1.Q IN_STATUS1.Q D1.PIN N_PZ_5587 SP_D1
---11 1
01--0 1
1-1-0 1
.names SP_IRQn
1
.names E_0_xpla_dummy_o_64.Q LED_0
0 1
.names SP_A1 D_0_TRIGADR_RD2.Q IN_STATUS2.Q D2.PIN N_PZ_5587 SP_D2
---11 1
01--0 1
1-1-0 1
.names SP_A21 A20
1 1
.names E_0_xpla_dummy_o_66.Q LED_1
0 1
.names SP_A1 D_0_TRIGADR_RD3.Q IN_STATUS3.Q D3.PIN N_PZ_5587 SP_D3
---11 1
01--0 1
1-1-0 1
.names SP_CS0n FLASH_CS0n
1 1
.names IO14.Q SP_A11 RAM_A10.Q A10
01- 1
1-1 1
.names E_0_xpla_dummy_o_68.Q LED_2
0 1
.names SP_RESETn RESET_MEMn
1 1
.names IO14.Q RAM_D0.Q SP_D0.PIN D0
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD4.Q IN_STATUS4.Q D4.PIN N_PZ_5587 SP_D4
---11 1
01--0 1
1-1-0 1
.names IO14.Q SP_CS1n SRAM_CS1n
01 1
.names IO14.Q SP_A12 RAM_A11.Q A11
01- 1
1-1 1
.names IO14.Q LED_3
0 1
.names IO14.Q RAM_D1.Q SP_D1.PIN D1
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD5.Q IN_STATUS5.Q D5.PIN N_PZ_5587 SP_D5
---11 1
01--0 1
1-1-0 1
.names IO14.Q SP_A13 RAM_A12.Q A12
01- 1
1-1 1
.names FLASH_W_PROTECTn
1
.names IO14.Q RAM_D10.Q SP_D10.PIN D10
11- 1
0-1 1
.names IO14.Q RAM_D2.Q SP_D2.PIN D2
11- 1
0-1 1
.names SP_A1 D_0_TRIGADR_RD6.Q IN_STATUS6.Q D6.PIN N_PZ_5587 SP_D6
---11 1
01--0 1
1-1-0 1
.names SP_A14 IO14.Q BANK0.Q A13
10- 1
-11 1
.names SP_WEn TRIGGER0.CLK
1 1
.names SP_WEn TRIGGER1.CLK
1 1
.names SP_WEn TRIGGER2.CLK
1 1
.names SP_WEn TRIGGER3.CLK
1 1
.names SP_WEn TRIGGER4.CLK
1 1
.names SP_WEn TRIGGER5.CLK
1 1
.names SP_WEn TRIGGER6.CLK
1 1
.names SP_WEn TRIGGER7.CLK
1 1
.names SP_WEn TRIGGER8.CLK
1 1
.names SP_WEn TRIGGER9.CLK
1 1
.names SP_WEn TRIGGER10.CLK
1 1
.names SP_WEn TRIGGER11.CLK
1 1
.names SP_WEn TRIGGER12.CLK
1 1
.names SP_WEn TRIGGER13.CLK
1 1
.names SP_WEn TRIGGER14.CLK
1 1
.names SP_WEn TRIGGER15.CLK
1 1
.names SP_WEn CNT_DWN0.CLK
1 1
.names SP_WEn CNT_DWN1.CLK
1 1
.names SP_WEn CNT_DWN2.CLK
1 1
.names SP_WEn CNT_DWN3.CLK
1 1
.names SP_WEn CNT_DWN4.CLK
1 1
.names SP_WEn CNT_DWN5.CLK
1 1
.names SP_WEn CNT_DWN6.CLK
1 1
.names SP_WEn CNT_DWN7.CLK
1 1
.names SP_WEn CNT_DWN8.CLK
1 1
.names SP_WEn CNT_DWN9.CLK
1 1
.names SP_WEn CNT_DWN10.CLK
1 1
.names SP_WEn CNT_DWN11.CLK
1 1
.names SP_WEn CNT_DWN12.CLK
1 1
.names SP_WEn SELCLK0.CLK
1 1
.names SP_WEn SELCLK1.CLK
1 1
.names SP_WEn SELCLK2.CLK
1 1
.names SP_WEn IO14.CLK
1 1
.names B_0_N133030.Q B_0_N133028.Q B_0_N133026.Q B_0_N133024.Q B_0_N133022.Q
B_0_N133020.Q B_0_N133018.Q B_0_N133062.Q B_0_N133060.Q B_0_N133058.Q
B_0_N139394.Q B_0_N139401.Q IO14.AR
000000000000 1
.names SP_WEn BANK0.CLK
1 1
.names SP_WEn BANK1.CLK
1 1
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