analyzer.bl3

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

#$ MODULE WREG0 
#$ PINS 34 REG0_CS SP_WEn SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 
#$ NODES 1 XPLA__dummy_o'co' 
.model WREG0 
.inputs REG0_CS SP_WEn SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 
.outputs CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 

# instance INST1 
.subckt DFFE D=SB_WD15 CLK=SP_WEn CE=REG0_CS Q=SELCLK2 QN=XPLA__dummy_o 

# instance INST2 
.subckt DFFE D=SB_WD14 CLK=SP_WEn CE=REG0_CS Q=SELCLK1 QN=XPLA__dummy_o 

# instance INST3 
.subckt DFFE D=SB_WD12 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN12 QN=XPLA__dummy_o 

# instance INST4 
.subckt DFFE D=SB_WD13 CLK=SP_WEn CE=REG0_CS Q=SELCLK0 QN=XPLA__dummy_o 

# instance INST5 
.subckt DFFE D=SB_WD11 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN11 QN=XPLA__dummy_o 

# instance INST6 
.subckt DFFE D=SB_WD10 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN10 QN=XPLA__dummy_o 

# instance INST7 
.subckt DFFE D=SB_WD9 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN9 QN=XPLA__dummy_o 

# instance INST8 
.subckt DFFE D=SB_WD8 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN8 QN=XPLA__dummy_o 

# instance INST9 
.subckt DFFE D=SB_WD7 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN7 QN=XPLA__dummy_o 

# instance INST10 
.subckt DFFE D=SB_WD6 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN6 QN=XPLA__dummy_o 

# instance INST11 
.subckt DFFE D=SB_WD5 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN5 QN=XPLA__dummy_o 

# instance INST12 
.subckt DFFE D=SB_WD4 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN4 QN=XPLA__dummy_o 

# instance INST13 
.subckt DFFE D=SB_WD3 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN3 QN=XPLA__dummy_o 

# instance INST14 
.subckt DFFE D=SB_WD2 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN2 QN=XPLA__dummy_o 

# instance INST15 
.subckt DFFE D=SB_WD1 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN1 QN=XPLA__dummy_o 

# instance INST16 
.subckt DFFE D=SB_WD0 CLK=SP_WEn CE=REG0_CS Q=CNT_DWN0 QN=XPLA__dummy_o 

.end 

#$ MODULE WREG6 
#$ PINS 29 REG6_CS SP_WEn CLR_RUN SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 LED_0 LED_1 LED_2 LED_3 RUN BANK0 BANK1 BANK2 BANK3 BANK4 
#$ NODES 1 XPLA__dummy_o'co' 
.model WREG6 
.inputs REG6_CS SP_WEn CLR_RUN SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 
.outputs LED_0 LED_1 LED_2 LED_3 RUN BANK0 BANK1 BANK2 BANK3 BANK4 

# instance INST60 
.subckt BUF IN0=SB_WD10 Z=XPLA__dummy_o 

# instance INST61 
.subckt BUF IN0=SB_WD11 Z=XPLA__dummy_o 

# instance INST62 
.subckt DFFE D=SB_WD12 CLK=SP_WEn CE=REG6_CS Q=XPLA__dummy_o QN=LED_0 

# instance INST63 
.subckt DFFE D=SB_WD4 CLK=SP_WEn CE=REG6_CS Q=BANK4 QN=XPLA__dummy_o 

# instance INST64 
.subckt DFFE D=SB_WD13 CLK=SP_WEn CE=REG6_CS Q=XPLA__dummy_o QN=LED_1 

# instance INST65 
.subckt DFFE D=SB_WD3 CLK=SP_WEn CE=REG6_CS Q=BANK3 QN=XPLA__dummy_o 

# instance INST66 
.subckt DFFE D=SB_WD14 CLK=SP_WEn CE=REG6_CS Q=XPLA__dummy_o QN=LED_2 

# instance INST67 
.subckt DFFE D=SB_WD2 CLK=SP_WEn CE=REG6_CS Q=BANK2 QN=XPLA__dummy_o 

# instance INST68 
.subckt DFFE D=SB_WD1 CLK=SP_WEn CE=REG6_CS Q=BANK1 QN=XPLA__dummy_o 

# instance INST69 
.subckt DFFRE D=SB_WD15 CLK=SP_WEn CE=REG6_CS RST=CLR_RUN Q=RUN QN=LED_3 

# instance INST70 
.subckt DFFE D=SB_WD0 CLK=SP_WEn CE=REG6_CS Q=BANK0 QN=XPLA__dummy_o 

# instance INST55 
.subckt BUF IN0=SB_WD5 Z=XPLA__dummy_o 

# instance INST56 
.subckt BUF IN0=SB_WD6 Z=XPLA__dummy_o 

# instance INST57 
.subckt BUF IN0=SB_WD7 Z=XPLA__dummy_o 

# instance INST58 
.subckt BUF IN0=SB_WD8 Z=XPLA__dummy_o 

# instance INST59 
.subckt BUF IN0=SB_WD9 Z=XPLA__dummy_o 

.end 

#$ MODULE REGISTERS 
#$ PINS 108 SP_A19 SP_CS1 SP_A1 SP_A2 SP_A3 SP_A4 SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 SP_WEn CLR_RUN TRIGADR_WR0 TRIGADR_WR1 TRIGADR_WR2 TRIGADR_WR3 TRIGADR_WR4 TRIGADR_WR5 TRIGADR_WR6 TRIGADR_WR7 TRIGADR_WR8 TRIGADR_WR9 TRIGADR_WR10 TRIGADR_WR11 TRIGADR_WR12 INPUT_HILO GOT_TRIG ACQ_RESET REG_SEL REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 LED_0 LED_1 LED_2 LED_3 CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 RUN BANK0 BANK1 BANK2 BANK3 BANK4 REG2_CS 
#$ NODES 22 REG0_CS'co' SP_A1N'co' N50598'co' SP_A4N'co' SP_A3N'co' REG4_CS'co' SP_A2N'co' REG6_CS'co' TRIG_HILO'co' TRIGADR_RD9'co' TRIGADR_RD8'co' TRIGADR_RD7'co' TRIGADR_RD6'co' TRIGADR_RD5'co' TRIGADR_RD4'co' TRIGADR_RD3'co' TRIGADR_RD2'co' TRIGADR_RD1'co' TRIGADR_RD0'co' TRIGADR_RD12'co' TRIGADR_RD11'co' TRIGADR_RD10'co' 
.model REGISTERS 
.inputs SP_A19 SP_CS1 SP_A1 SP_A2 SP_A3 SP_A4 SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 SP_WEn CLR_RUN TRIGADR_WR0 TRIGADR_WR1 TRIGADR_WR2 TRIGADR_WR3 TRIGADR_WR4 TRIGADR_WR5 TRIGADR_WR6 TRIGADR_WR7 TRIGADR_WR8 TRIGADR_WR9 TRIGADR_WR10 TRIGADR_WR11 TRIGADR_WR12 INPUT_HILO GOT_TRIG ACQ_RESET 
.outputs REG_SEL REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 LED_0 LED_1 LED_2 LED_3 CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 RUN BANK0 BANK1 BANK2 BANK3 BANK4 REG2_CS 

# instance INST120 
.subckt AND5 IN0=REG_SEL IN1=SP_A1N IN2=SP_A2 IN3=SP_A3N IN4=SP_A4N Z=REG4_CS 

# instance INST121 
.subckt AND5 IN0=REG_SEL IN1=SP_A1 IN2=SP_A2 IN3=SP_A3N IN4=SP_A4N Z=REG6_CS 

# instance INST122 
.subckt AND2 IN0=SP_CS1 IN1=N50598 Z=REG_SEL 

# instance INST118 
.subckt AND5 IN0=REG_SEL IN1=SP_A1N IN2=SP_A2N IN3=SP_A3N IN4=SP_A4N Z=REG0_CS 

# instance INST119 
.subckt AND5 IN0=REG_SEL IN1=SP_A1 IN2=SP_A2N IN3=SP_A3N IN4=SP_A4N Z=REG2_CS 

# instance WREG0 
.subckt WREG0 REG0_CS=REG0_CS SP_WEn=SP_WEn SB_WD0=SB_WD0 SB_WD1=SB_WD1 SB_WD2=SB_WD2 SB_WD3=SB_WD3 SB_WD4=SB_WD4 SB_WD5=SB_WD5 SB_WD6=SB_WD6 SB_WD7=SB_WD7 SB_WD8=SB_WD8 SB_WD9=SB_WD9 SB_WD10=SB_WD10 SB_WD11=SB_WD11 SB_WD12=SB_WD12 SB_WD13=SB_WD13 SB_WD14=SB_WD14 SB_WD15=SB_WD15 CNT_DWN0=CNT_DWN0 CNT_DWN1=CNT_DWN1 CNT_DWN2=CNT_DWN2 CNT_DWN3=CNT_DWN3 CNT_DWN4=CNT_DWN4 CNT_DWN5=CNT_DWN5 CNT_DWN6=CNT_DWN6 CNT_DWN7=CNT_DWN7 CNT_DWN8=CNT_DWN8 CNT_DWN9=CNT_DWN9 CNT_DWN10=CNT_DWN10 CNT_DWN11=CNT_DWN11 CNT_DWN12=CNT_DWN12 SELCLK0=SELCLK0 SELCLK1=SELCLK1 SELCLK2=SELCLK2 

# instance WREG4 
.subckt WREG4 REG4_CS=REG4_CS SP_WEn=SP_WEn SB_WD0=SB_WD0 SB_WD1=SB_WD1 SB_WD2=SB_WD2 SB_WD3=SB_WD3 SB_WD4=SB_WD4 SB_WD5=SB_WD5 SB_WD6=SB_WD6 SB_WD7=SB_WD7 SB_WD8=SB_WD8 SB_WD9=SB_WD9 SB_WD10=SB_WD10 SB_WD11=SB_WD11 SB_WD12=SB_WD12 SB_WD13=SB_WD13 SB_WD14=SB_WD14 SB_WD15=SB_WD15 TRIGGER0=TRIGGER0 TRIGGER1=TRIGGER1 TRIGGER2=TRIGGER2 TRIGGER3=TRIGGER3 TRIGGER4=TRIGGER4 TRIGGER5=TRIGGER5 TRIGGER6=TRIGGER6 TRIGGER7=TRIGGER7 TRIGGER8=TRIGGER8 TRIGGER9=TRIGGER9 TRIGGER10=TRIGGER10 TRIGGER11=TRIGGER11 TRIGGER12=TRIGGER12 TRIGGER13=TRIGGER13 TRIGGER14=TRIGGER14 TRIGGER15=TRIGGER15 

# instance WREG6 
.subckt WREG6 REG6_CS=REG6_CS SP_WEn=SP_WEn CLR_RUN=CLR_RUN SB_WD0=SB_WD0 SB_WD1=SB_WD1 SB_WD2=SB_WD2 SB_WD3=SB_WD3 SB_WD4=SB_WD4 SB_WD5=SB_WD5 SB_WD6=SB_WD6 SB_WD7=SB_WD7 SB_WD8=SB_WD8 SB_WD9=SB_WD9 SB_WD10=SB_WD10 SB_WD11=SB_WD11 SB_WD12=SB_WD12 SB_WD13=SB_WD13 SB_WD14=SB_WD14 SB_WD15=SB_WD15 LED_0=LED_0 LED_1=LED_1 LED_2=LED_2 LED_3=LED_3 RUN=RUN BANK0=BANK0 BANK1=BANK1 BANK2=BANK2 BANK3=BANK3 BANK4=BANK4 

# instance REG_READSEL 
.subckt REG_READSEL IN_STATUS0=IN_STATUS0 IN_STATUS1=IN_STATUS1 IN_STATUS2=IN_STATUS2 IN_STATUS3=IN_STATUS3 IN_STATUS4=IN_STATUS4 IN_STATUS5=IN_STATUS5 IN_STATUS6=IN_STATUS6 IN_STATUS7=IN_STATUS7 TRIG_HILO=TRIG_HILO TRIGADR_RD0=TRIGADR_RD0 TRIGADR_RD1=TRIGADR_RD1 TRIGADR_RD2=TRIGADR_RD2 TRIGADR_RD3=TRIGADR_RD3 TRIGADR_RD4=TRIGADR_RD4 TRIGADR_RD5=TRIGADR_RD5 TRIGADR_RD6=TRIGADR_RD6 TRIGADR_RD7=TRIGADR_RD7 TRIGADR_RD8=TRIGADR_RD8 TRIGADR_RD9=TRIGADR_RD9 TRIGADR_RD10=TRIGADR_RD10 TRIGADR_RD11=TRIGADR_RD11 TRIGADR_RD12=TRIGADR_RD12 GOT_TRIG=GOT_TRIG SP_A1=SP_A1 RUN=RUN REG_RD0=REG_RD0 REG_RD1=REG_RD1 REG_RD2=REG_RD2 REG_RD3=REG_RD3 REG_RD4=REG_RD4 REG_RD5=REG_RD5 REG_RD6=REG_RD6 REG_RD7=REG_RD7 REG_RD8=REG_RD8 REG_RD9=REG_RD9 REG_RD10=REG_RD10 REG_RD11=REG_RD11 REG_RD12=REG_RD12 REG_RD13=REG_RD13 REG_RD14=REG_RD14 REG_RD15=REG_RD15 

# instance RREG0 
.subckt RREG0 TRIGADR_WR0=TRIGADR_WR0 TRIGADR_WR1=TRIGADR_WR1 TRIGADR_WR2=TRIGADR_WR2 TRIGADR_WR3=TRIGADR_WR3 TRIGADR_WR4=TRIGADR_WR4 TRIGADR_WR5=TRIGADR_WR5 TRIGADR_WR6=TRIGADR_WR6 TRIGADR_WR7=TRIGADR_WR7 TRIGADR_WR8=TRIGADR_WR8 TRIGADR_WR9=TRIGADR_WR9 TRIGADR_WR10=TRIGADR_WR10 TRIGADR_WR11=TRIGADR_WR11 TRIGADR_WR12=TRIGADR_WR12 INPUT_HILO=INPUT_HILO ACQ_RESET=ACQ_RESET GOT_TRIG=GOT_TRIG TRIGADR_RD0=TRIGADR_RD0 TRIGADR_RD1=TRIGADR_RD1 TRIGADR_RD2=TRIGADR_RD2 TRIGADR_RD3=TRIGADR_RD3 TRIGADR_RD4=TRIGADR_RD4 TRIGADR_RD5=TRIGADR_RD5 TRIGADR_RD6=TRIGADR_RD6 TRIGADR_RD7=TRIGADR_RD7 TRIGADR_RD8=TRIGADR_RD8 TRIGADR_RD9=TRIGADR_RD9 TRIGADR_RD10=TRIGADR_RD10 TRIGADR_RD11=TRIGADR_RD11 TRIGADR_RD12=TRIGADR_RD12 TRIG_HILO=TRIG_HILO 

# instance INST123 of cell INV 
.names SP_A19 N50598 
0 1 

# instance INST124 of cell INV 
.names SP_A1 SP_A1N 
0 1 

# instance INST125 of cell INV 
.names SP_A2 SP_A2N 
0 1 

# instance INST126 of cell INV 
.names SP_A3 SP_A3N 
0 1 

# instance INST127 of cell INV 
.names SP_A4 SP_A4N 
0 1 

.end 

#$ MODULE ADDRESS_BUS 
#$ PINS 61 RAM_A0 RAM_A1 RAM_A2 RAM_A3 RAM_A4 RAM_A5 RAM_A6 RAM_A7 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_A12 RAM_A13 RAM_A14 RAM_A15 RAM_A16 RAM_A17 RUN SP_A1 SP_A2 SP_A3 SP_A4 SP_A5 SP_A6 SP_A7 SP_A8 SP_A9 SP_A10 SP_A11 SP_A12 SP_A13 SP_A14 SP_A15 SP_A16 SP_A17 SP_A18 SP_A19 SP_A20 SP_A21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 
.model ADDRESS_BUS 
.inputs RAM_A0 RAM_A1 RAM_A2 RAM_A3 RAM_A4 RAM_A5 RAM_A6 RAM_A7 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_A12 RAM_A13 RAM_A14 RAM_A15 RAM_A16 RAM_A17 RUN SP_A1 SP_A2 SP_A3 SP_A4 SP_A5 SP_A6 SP_A7 SP_A8 SP_A9 SP_A10 SP_A11 SP_A12 SP_A13 SP_A14 SP_A15 SP_A16 SP_A17 SP_A18 SP_A19 SP_A20 SP_A21 
.outputs A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 

# instance U45 
.subckt MUX21 SEL=RUN IN0=SP_A16 IN1=RAM_A15 Z=A15 

# instance U28 
.subckt MUX21 SEL=RUN IN0=SP_A1 IN1=RAM_A0 Z=A0 

# instance U29 
.subckt MUX21 SEL=RUN IN0=SP_A2 IN1=RAM_A1 Z=A1 

# instance U30 
.subckt MUX21 SEL=RUN IN0=SP_A3 IN1=RAM_A2 Z=A2 

# instance U31 
.subckt MUX21 SEL=RUN IN0=SP_A4 IN1=RAM_A3 Z=A3 

# instance U32 
.subckt MUX21 SEL=RUN IN0=SP_A17 IN1=RAM_A16 Z=A16 

# instance U33 
.subckt MUX21 SEL=RUN IN0=SP_A18 IN1=RAM_A17 Z=A17 

# instance U34 
.subckt MUX21 SEL=RUN IN0=SP_A5 IN1=RAM_A4 Z=A4 

# instance U35 
.subckt MUX21 SEL=RUN IN0=SP_A6 IN1=RAM_A5 Z=A5 

# instance U36 
.subckt MUX21 SEL=RUN IN0=SP_A7 IN1=RAM_A6 Z=A6 

# instance U37 
.subckt MUX21 SEL=RUN IN0=SP_A8 IN1=RAM_A7 Z=A7 

# instance U38 
.subckt MUX21 SEL=RUN IN0=SP_A9 IN1=RAM_A8 Z=A8 

# instance U39 
.subckt MUX21 SEL=RUN IN0=SP_A10 IN1=RAM_A9 Z=A9 

# instance INST52 
.subckt BUF IN0=SP_A19 Z=A18 

# instance INST53 
.subckt BUF IN0=SP_A20 Z=A19 

# instance INST54 
.subckt BUF IN0=SP_A21 Z=A20 

# instance U40 
.subckt MUX21 SEL=RUN IN0=SP_A11 IN1=RAM_A10 Z=A10 

# instance U41 
.subckt MUX21 SEL=RUN IN0=SP_A12 IN1=RAM_A11 Z=A11 

# instance U42 
.subckt MUX21 SEL=RUN IN0=SP_A13 IN1=RAM_A12 Z=A12 

# instance U43 
.subckt MUX21 SEL=RUN IN0=SP_A14 IN1=RAM_A13 Z=A13 

# instance U44 
.subckt MUX21 SEL=RUN IN0=SP_A15 IN1=RAM_A14 Z=A14 

.end