analyzer.bl3

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

# instance U63 
.subckt MUX21 SEL=RUN IN0=SB_WD8 IN1=RAM_D8 Z=MEM_WD8 

# instance U64 
.subckt MUX21 SEL=RUN IN0=SB_WD9 IN1=RAM_D9 Z=MEM_WD9 

# instance U65 
.subckt MUX21 SEL=RUN IN0=SB_WD10 IN1=RAM_D10 Z=MEM_WD10 

# instance U66 
.subckt MUX21 SEL=RUN IN0=SB_WD11 IN1=RAM_D11 Z=MEM_WD11 

# instance U67 
.subckt MUX21 SEL=RUN IN0=SB_WD12 IN1=RAM_D12 Z=MEM_WD12 

# instance U68 
.subckt MUX21 SEL=RUN IN0=SB_WD13 IN1=RAM_D13 Z=MEM_WD13 

# instance U69 
.subckt MUX21 SEL=RUN IN0=SB_WD14 IN1=RAM_D14 Z=MEM_WD14 

# instance U70 
.subckt MUX21 SEL=RUN IN0=SB_WD15 IN1=RAM_D15 Z=MEM_WD15 

.end 

#$ MODULE DATA_BUS 
#$ PINS 86 SP_CS0 SP_CS1 SP_OE SP_WE RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 RUN REG_SEL SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 SP_D0 SP_D1 SP_D2 SP_D3 SP_D4 SP_D5 SP_D6 SP_D7 SP_D8 SP_D9 SP_D10 SP_D11 SP_D12 SP_D13 SP_D14 SP_D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 
#$ NODES 56 READ_ENABLE'co' N32762'co' MEM_WD1'co' MEM_WD7'co' MEM_WD3'co' MEM_WD4'co' MEM_WD2'co' N51515'co' N34481'co' N51332'co' N511272'co' WRITE_ENABLE'co' MEM_WD5'co' MEM_WD11'co' MEM_WD9'co' MEM_WD10'co' MEM_WD12'co' MEM_WD15'co' MEM_WD14'co' MEM_WD8'co' MEM_WD0'co' MEM_WD13'co' MEM_WD6'co' MEM_RD1'co' MEM_RD2'co' MEM_RD10'co' MEM_RD15'co' MEM_RD11'co' MEM_RD13'co' MEM_RD5'co' SB_RD1'co' SB_RD0'co' SB_RD12'co' SB_RD10'co' SB_RD11'co' SB_RD8'co' SB_RD9'co' MEM_RD0'co' MEM_RD4'co' MEM_RD8'co' MEM_RD6'co' MEM_RD12'co' MEM_RD7'co' MEM_RD9'co' MEM_RD3'co' MEM_RD14'co' SB_RD3'co' SB_RD5'co' SB_RD7'co' SB_RD4'co' SB_RD6'co' SB_RD2'co' SB_RD14'co' SB_RD13'co' SB_RD15'co' N50652'co' 
.model DATA_BUS 
.inputs SP_CS0 SP_CS1 SP_OE SP_WE RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 RUN REG_SEL 
.outputs SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 SP_D0 SP_D1 SP_D2 SP_D3 SP_D4 SP_D5 SP_D6 SP_D7 SP_D8 SP_D9 SP_D10 SP_D11 SP_D12 SP_D13 SP_D14 SP_D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 

# instance U1 
.subckt TRI16 E=WRITE_ENABLE IN0=MEM_WD0 IN1=MEM_WD1 IN2=MEM_WD2 IN3=MEM_WD3 IN4=MEM_WD4 IN5=MEM_WD5 IN6=MEM_WD6 IN7=MEM_WD7 IN8=MEM_WD8 IN9=MEM_WD9 IN10=MEM_WD10 IN11=MEM_WD11 IN12=MEM_WD12 IN13=MEM_WD13 IN14=MEM_WD14 IN15=MEM_WD15 O0=D0 O1=D1 O2=D2 O3=D3 O4=D4 O5=D5 O6=D6 O7=D7 O8=D8 O9=D9 O10=D10 O11=D11 O12=D12 O13=D13 O14=D14 O15=D15 

# instance U2 
.subckt BUF16 IN0=SP_D0 IN1=SP_D1 IN2=SP_D2 IN3=SP_D3 IN4=SP_D4 IN5=SP_D5 IN6=SP_D6 IN7=SP_D7 IN8=SP_D8 IN9=SP_D9 IN10=SP_D10 IN11=SP_D11 IN12=SP_D12 IN13=SP_D13 IN14=SP_D14 IN15=SP_D15 Z0=SB_WD0 Z1=SB_WD1 Z2=SB_WD2 Z3=SB_WD3 Z4=SB_WD4 Z5=SB_WD5 Z6=SB_WD6 Z7=SB_WD7 Z8=SB_WD8 Z9=SB_WD9 Z10=SB_WD10 Z11=SB_WD11 Z12=SB_WD12 Z13=SB_WD13 Z14=SB_WD14 Z15=SB_WD15 

# instance U3 
.subckt TRI16 E=READ_ENABLE IN0=SB_RD0 IN1=SB_RD1 IN2=SB_RD2 IN3=SB_RD3 IN4=SB_RD4 IN5=SB_RD5 IN6=SB_RD6 IN7=SB_RD7 IN8=SB_RD8 IN9=SB_RD9 IN10=SB_RD10 IN11=SB_RD11 IN12=SB_RD12 IN13=SB_RD13 IN14=SB_RD14 IN15=SB_RD15 O0=SP_D0 O1=SP_D1 O2=SP_D2 O3=SP_D3 O4=SP_D4 O5=SP_D5 O6=SP_D6 O7=SP_D7 O8=SP_D8 O9=SP_D9 O10=SP_D10 O11=SP_D11 O12=SP_D12 O13=SP_D13 O14=SP_D14 O15=SP_D15 

# instance U4 
.subckt BUF16 IN0=D0 IN1=D1 IN2=D2 IN3=D3 IN4=D4 IN5=D5 IN6=D6 IN7=D7 IN8=D8 IN9=D9 IN10=D10 IN11=D11 IN12=D12 IN13=D13 IN14=D14 IN15=D15 Z0=MEM_RD0 Z1=MEM_RD1 Z2=MEM_RD2 Z3=MEM_RD3 Z4=MEM_RD4 Z5=MEM_RD5 Z6=MEM_RD6 Z7=MEM_RD7 Z8=MEM_RD8 Z9=MEM_RD9 Z10=MEM_RD10 Z11=MEM_RD11 Z12=MEM_RD12 Z13=MEM_RD13 Z14=MEM_RD14 Z15=MEM_RD15 

# instance INST17 
.subckt OR2 IN0=SP_CS0 IN1=SP_CS1 Z=N32762 

# instance INST18 
.subckt AND2 IN0=REG_SEL IN1=SP_OE Z=N50652 

# instance INST19 
.subckt AND2 IN0=N32762 IN1=SP_OE Z=READ_ENABLE 

# instance INST20 
.subckt OR2 IN0=SP_CS0 IN1=N51332 Z=N34481 

# instance INST21 
.subckt AND2 IN0=SP_CS1 IN1=N511272 Z=N51332 

# instance INST22 
.subckt AND2 IN0=N34481 IN1=SP_WE Z=N51515 

# instance INST24 
.subckt OR2 IN0=N51515 IN1=RUN Z=WRITE_ENABLE 

# instance SB_R_DATA 
.subckt SB_R_DATA REG_RD=N50652 MEM_RD0=MEM_RD0 MEM_RD1=MEM_RD1 MEM_RD2=MEM_RD2 MEM_RD3=MEM_RD3 MEM_RD4=MEM_RD4 MEM_RD5=MEM_RD5 MEM_RD6=MEM_RD6 MEM_RD7=MEM_RD7 MEM_RD8=MEM_RD8 MEM_RD9=MEM_RD9 MEM_RD10=MEM_RD10 MEM_RD11=MEM_RD11 MEM_RD12=MEM_RD12 MEM_RD13=MEM_RD13 MEM_RD14=MEM_RD14 MEM_RD15=MEM_RD15 REG_RD0=REG_RD0 REG_RD1=REG_RD1 REG_RD2=REG_RD2 REG_RD3=REG_RD3 REG_RD4=REG_RD4 REG_RD5=REG_RD5 REG_RD6=REG_RD6 REG_RD7=REG_RD7 REG_RD8=REG_RD8 REG_RD9=REG_RD9 REG_RD10=REG_RD10 REG_RD11=REG_RD11 REG_RD12=REG_RD12 REG_RD13=REG_RD13 REG_RD14=REG_RD14 REG_RD15=REG_RD15 SB_RD0=SB_RD0 SB_RD1=SB_RD1 SB_RD2=SB_RD2 SB_RD3=SB_RD3 SB_RD4=SB_RD4 SB_RD5=SB_RD5 SB_RD6=SB_RD6 SB_RD7=SB_RD7 SB_RD8=SB_RD8 SB_RD9=SB_RD9 SB_RD10=SB_RD10 SB_RD11=SB_RD11 SB_RD12=SB_RD12 SB_RD13=SB_RD13 SB_RD14=SB_RD14 SB_RD15=SB_RD15 

# instance RAM_W_DATA 
.subckt RAM_W_DATA SB_WD0=SB_WD0 SB_WD1=SB_WD1 SB_WD2=SB_WD2 SB_WD3=SB_WD3 SB_WD4=SB_WD4 SB_WD5=SB_WD5 SB_WD6=SB_WD6 SB_WD7=SB_WD7 SB_WD8=SB_WD8 SB_WD9=SB_WD9 SB_WD10=SB_WD10 SB_WD11=SB_WD11 SB_WD12=SB_WD12 SB_WD13=SB_WD13 SB_WD14=SB_WD14 SB_WD15=SB_WD15 RAM_D0=RAM_D0 RAM_D1=RAM_D1 RAM_D2=RAM_D2 RAM_D3=RAM_D3 RAM_D4=RAM_D4 RAM_D5=RAM_D5 RAM_D6=RAM_D6 RAM_D7=RAM_D7 RAM_D8=RAM_D8 RAM_D9=RAM_D9 RAM_D10=RAM_D10 RAM_D11=RAM_D11 RAM_D12=RAM_D12 RAM_D13=RAM_D13 RAM_D14=RAM_D14 RAM_D15=RAM_D15 RUN=RUN MEM_WD0=MEM_WD0 MEM_WD1=MEM_WD1 MEM_WD2=MEM_WD2 MEM_WD3=MEM_WD3 MEM_WD4=MEM_WD4 MEM_WD5=MEM_WD5 MEM_WD6=MEM_WD6 MEM_WD7=MEM_WD7 MEM_WD8=MEM_WD8 MEM_WD9=MEM_WD9 MEM_WD10=MEM_WD10 MEM_WD11=MEM_WD11 MEM_WD12=MEM_WD12 MEM_WD13=MEM_WD13 MEM_WD14=MEM_WD14 MEM_WD15=MEM_WD15 

# instance INST23 of cell INV 
.names REG_SEL N511272 
0 1 

.end 

#$ MODULE RREG0 
#$ PINS 30 TRIGADR_WR0 TRIGADR_WR1 TRIGADR_WR2 TRIGADR_WR3 TRIGADR_WR4 TRIGADR_WR5 TRIGADR_WR6 TRIGADR_WR7 TRIGADR_WR8 TRIGADR_WR9 TRIGADR_WR10 TRIGADR_WR11 TRIGADR_WR12 INPUT_HILO ACQ_RESET GOT_TRIG TRIGADR_RD0 TRIGADR_RD1 TRIGADR_RD2 TRIGADR_RD3 TRIGADR_RD4 TRIGADR_RD5 TRIGADR_RD6 TRIGADR_RD7 TRIGADR_RD8 TRIGADR_RD9 TRIGADR_RD10 TRIGADR_RD11 TRIGADR_RD12 TRIG_HILO 
#$ NODES 1 XPLA__dummy_o'co' 
.model RREG0 
.inputs TRIGADR_WR0 TRIGADR_WR1 TRIGADR_WR2 TRIGADR_WR3 TRIGADR_WR4 TRIGADR_WR5 TRIGADR_WR6 TRIGADR_WR7 TRIGADR_WR8 TRIGADR_WR9 TRIGADR_WR10 TRIGADR_WR11 TRIGADR_WR12 INPUT_HILO ACQ_RESET GOT_TRIG 
.outputs TRIGADR_RD0 TRIGADR_RD1 TRIGADR_RD2 TRIGADR_RD3 TRIGADR_RD4 TRIGADR_RD5 TRIGADR_RD6 TRIGADR_RD7 TRIGADR_RD8 TRIGADR_RD9 TRIGADR_RD10 TRIGADR_RD11 TRIGADR_RD12 TRIG_HILO 

# instance INST128 
.subckt DFFR D=INPUT_HILO CLK=GOT_TRIG RST=ACQ_RESET Q=TRIG_HILO QN=XPLA__dummy_o 

# instance INST129 
.subckt DFFR D=TRIGADR_WR12 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD12 QN=XPLA__dummy_o 

# instance INST130 
.subckt DFFR D=TRIGADR_WR11 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD11 QN=XPLA__dummy_o 

# instance INST131 
.subckt DFFR D=TRIGADR_WR10 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD10 QN=XPLA__dummy_o 

# instance INST132 
.subckt DFFR D=TRIGADR_WR9 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD9 QN=XPLA__dummy_o 

# instance INST133 
.subckt DFFR D=TRIGADR_WR8 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD8 QN=XPLA__dummy_o 

# instance INST134 
.subckt DFFR D=TRIGADR_WR7 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD7 QN=XPLA__dummy_o 

# instance INST135 
.subckt DFFR D=TRIGADR_WR6 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD6 QN=XPLA__dummy_o 

# instance INST136 
.subckt DFFR D=TRIGADR_WR5 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD5 QN=XPLA__dummy_o 

# instance INST137 
.subckt DFFR D=TRIGADR_WR4 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD4 QN=XPLA__dummy_o 

# instance INST138 
.subckt DFFR D=TRIGADR_WR3 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD3 QN=XPLA__dummy_o 

# instance INST139 
.subckt DFFR D=TRIGADR_WR2 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD2 QN=XPLA__dummy_o 

# instance INST140 
.subckt DFFR D=TRIGADR_WR1 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD1 QN=XPLA__dummy_o 

# instance INST141 
.subckt DFFR D=TRIGADR_WR0 CLK=GOT_TRIG RST=ACQ_RESET Q=TRIGADR_RD0 QN=XPLA__dummy_o 

.end 

#$ MODULE REG_READSEL 
#$ PINS 41 IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 TRIG_HILO TRIGADR_RD0 TRIGADR_RD1 TRIGADR_RD2 TRIGADR_RD3 TRIGADR_RD4 TRIGADR_RD5 TRIGADR_RD6 TRIGADR_RD7 TRIGADR_RD8 TRIGADR_RD9 TRIGADR_RD10 TRIGADR_RD11 TRIGADR_RD12 GOT_TRIG SP_A1 RUN REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 
#$ NODES 2 N197429'co' N197470'co' 
.model REG_READSEL 
.inputs IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 TRIG_HILO TRIGADR_RD0 TRIGADR_RD1 TRIGADR_RD2 TRIGADR_RD3 TRIGADR_RD4 TRIGADR_RD5 TRIGADR_RD6 TRIGADR_RD7 TRIGADR_RD8 TRIGADR_RD9 TRIGADR_RD10 TRIGADR_RD11 TRIGADR_RD12 GOT_TRIG SP_A1 RUN 
.outputs REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 

# instance U77 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD1 IN1=IN_STATUS1 Z=REG_RD1 

# instance U78 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD5 IN1=IN_STATUS5 Z=REG_RD5 

# instance U79 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD9 IN1=N197429 Z=REG_RD9 

# instance U80 
.subckt MUX21 SEL=SP_A1 IN0=TRIG_HILO IN1=N197470 Z=REG_RD13 

# instance U81 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD2 IN1=IN_STATUS2 Z=REG_RD2 

# instance U82 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD6 IN1=IN_STATUS6 Z=REG_RD6 

# instance U83 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD10 IN1=N197429 Z=REG_RD10 

# instance U84 
.subckt MUX21 SEL=SP_A1 IN0=GOT_TRIG IN1=N197470 Z=REG_RD14 

# instance U85 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD3 IN1=IN_STATUS3 Z=REG_RD3 

# instance U86 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD7 IN1=IN_STATUS7 Z=REG_RD7 

# instance U87 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD11 IN1=N197429 Z=REG_RD11 

# instance U88 
.subckt MUX21 SEL=SP_A1 IN0=RUN IN1=N197470 Z=REG_RD15 

# instance U89 
.subckt GND O=N197429 

# instance U90 
.subckt GND O=N197470 

# instance U73 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD0 IN1=IN_STATUS0 Z=REG_RD0 

# instance U74 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD4 IN1=IN_STATUS4 Z=REG_RD4 

# instance U75 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD8 IN1=N197429 Z=REG_RD8 

# instance U76 
.subckt MUX21 SEL=SP_A1 IN0=TRIGADR_RD12 IN1=N197470 Z=REG_RD12 

.end 

#$ MODULE WREG4 
#$ PINS 34 REG4_CS SP_WEn SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 
#$ NODES 1 XPLA__dummy_o'co' 
.model WREG4 
.inputs REG4_CS SP_WEn SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 
.outputs TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 

# instance INST30 
.subckt DFFE D=SB_WD10 CLK=SP_WEn CE=REG4_CS Q=TRIGGER10 QN=XPLA__dummy_o 

# instance INST31 
.subckt DFFE D=SB_WD9 CLK=SP_WEn CE=REG4_CS Q=TRIGGER9 QN=XPLA__dummy_o 

# instance INST32 
.subckt DFFE D=SB_WD8 CLK=SP_WEn CE=REG4_CS Q=TRIGGER8 QN=XPLA__dummy_o 

# instance INST33 
.subckt DFFE D=SB_WD7 CLK=SP_WEn CE=REG4_CS Q=TRIGGER7 QN=XPLA__dummy_o 

# instance INST34 
.subckt DFFE D=SB_WD6 CLK=SP_WEn CE=REG4_CS Q=TRIGGER6 QN=XPLA__dummy_o 

# instance INST35 
.subckt DFFE D=SB_WD5 CLK=SP_WEn CE=REG4_CS Q=TRIGGER5 QN=XPLA__dummy_o 

# instance INST36 
.subckt DFFE D=SB_WD4 CLK=SP_WEn CE=REG4_CS Q=TRIGGER4 QN=XPLA__dummy_o 

# instance INST37 
.subckt DFFE D=SB_WD3 CLK=SP_WEn CE=REG4_CS Q=TRIGGER3 QN=XPLA__dummy_o 

# instance INST38 
.subckt DFFE D=SB_WD2 CLK=SP_WEn CE=REG4_CS Q=TRIGGER2 QN=XPLA__dummy_o 

# instance INST39 
.subckt DFFE D=SB_WD1 CLK=SP_WEn CE=REG4_CS Q=TRIGGER1 QN=XPLA__dummy_o 

# instance INST40 
.subckt DFFE D=SB_WD0 CLK=SP_WEn CE=REG4_CS Q=TRIGGER0 QN=XPLA__dummy_o 

# instance INST25 
.subckt DFFE D=SB_WD15 CLK=SP_WEn CE=REG4_CS Q=TRIGGER15 QN=XPLA__dummy_o 

# instance INST26 
.subckt DFFE D=SB_WD14 CLK=SP_WEn CE=REG4_CS Q=TRIGGER14 QN=XPLA__dummy_o 

# instance INST27 
.subckt DFFE D=SB_WD12 CLK=SP_WEn CE=REG4_CS Q=TRIGGER12 QN=XPLA__dummy_o 

# instance INST28 
.subckt DFFE D=SB_WD13 CLK=SP_WEn CE=REG4_CS Q=TRIGGER13 QN=XPLA__dummy_o 

# instance INST29 
.subckt DFFE D=SB_WD11 CLK=SP_WEn CE=REG4_CS Q=TRIGGER11 QN=XPLA__dummy_o 

.end