analyzer.bl3

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

.subckt DFFRE D=XPLANOT__SYS_CLK4 CLK=SYS_CLK2.Q CE=RUN RST=ACQ_RESET Q=SYS_CLK4 QN=N125990 

# instance INST72 
.subckt DFFRE D=XPLANOT__SYS_CLK2 CLK=SYS_CLK CE=RUN RST=ACQ_RESET Q=SYS_CLK2 QN=N125972 

# instance INST73 
.subckt AND2 IN0=RUN IN1=SELCLK2 Z=N136442 

# instance INST74 
.subckt AND5B5 IN0=N133197 IN1=N133234 IN2=N133052 IN3=N133054 IN4=N133056 Z=N133212 

# instance INST75 
.subckt AND5B5 IN0=N133058 IN1=N133060 IN2=N133062 IN3=N133018 IN4=N133020 Z=N1331745 

# instance INST76 
.subckt AND3 IN0=N133212 IN1=N1331745 IN2=N133215 Z=N133409 

# instance INST77 
.subckt DFFE D=N133409 CLK=SYS_CLK CE=N133441 Q=DWN_OUT QN=XPLA__dummy_o 

# instance INST78 
.subckt AND5B5 IN0=N133022 IN1=N133024 IN2=N133026 IN3=N133028 IN4=N133030 Z=N133215 

# instance INST79 
.subckt AND2 IN0=RUN IN1=SELCLK2 Z=N133441 

.names SYS_CLK4.Q XPLANOT__SYS_CLK4
0 1

.names SYS_CLK2.Q XPLANOT__SYS_CLK2
0 1

.end 

#$ MODULE ACQ_CONTROL 
#$ PINS 126 BANK0 BANK1 BANK2 BANK3 BANK4 TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 RUN CH_IN0 CH_IN1 CH_IN2 CH_IN3 CH_IN4 CH_IN5 CH_IN6 CH_IN7 SYS_CLK CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 SP_OE REG2_CS SP_WEn SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 ACQ_RESET INPUT_HILO GOT_TRIG IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 TRIGADR_WR0 TRIGADR_WR1 TRIGADR_WR2 TRIGADR_WR3 TRIGADR_WR4 TRIGADR_WR5 TRIGADR_WR6 TRIGADR_WR7 TRIGADR_WR8 TRIGADR_WR9 TRIGADR_WR10 TRIGADR_WR11 TRIGADR_WR12 RAM_A0 RAM_A1 RAM_A2 RAM_A3 RAM_A4 RAM_A5 RAM_A6 RAM_A7 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_A12 RAM_A13 RAM_A14 RAM_A15 RAM_A16 RAM_A17 CLR_RUN ACQ_WRn 
#$ NODES 26 STOP'co' N177828'co' N177842'co' N182139'co' N183049'co' ACQ_BEGIN'co' N136978'co' N139448'co' N139441'co' N160724'co' SAMPL_CLK'co' N133030'co' N182142'co' N133026'co' N139401'co' N139394'co' N133062'co' N133022'co' N133018'co' N133058'co' N133028'co' N133024'co' N133020'co' N133060'co' N131094'co' XPLA__dummy_o'co' 
.model ACQ_CONTROL 
.inputs BANK0 BANK1 BANK2 BANK3 BANK4 TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 RUN CH_IN0 CH_IN1 CH_IN2 CH_IN3 CH_IN4 CH_IN5 CH_IN6 CH_IN7 SYS_CLK CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 SP_OE REG2_CS SP_WEn SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 GOT_TRIG.Q 
.outputs ACQ_RESET INPUT_HILO GOT_TRIG IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 TRIGADR_WR0 TRIGADR_WR1 TRIGADR_WR2 TRIGADR_WR3 TRIGADR_WR4 TRIGADR_WR5 TRIGADR_WR6 TRIGADR_WR7 TRIGADR_WR8 TRIGADR_WR9 TRIGADR_WR10 TRIGADR_WR11 TRIGADR_WR12 RAM_A0 RAM_A1 RAM_A2 RAM_A3 RAM_A4 RAM_A5 RAM_A6 RAM_A7 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_A12 RAM_A13 RAM_A14 RAM_A15 RAM_A16 RAM_A17 CLR_RUN ACQ_WRn 

# instance INST90 
.subckt BUF IN0=SB_WD15 Z=XPLA__dummy_o 

# instance INST91 
.subckt BUF IN0=INPUT_HILO Z=ACQ_WRn 

# instance INST92 
.subckt DFFR D=N177828 CLK=N177842 RST=STOP Q=GOT_TRIG QN=XPLA__dummy_o 

# instance INST94 
.subckt BUF IN0=RAM_A0 Z=TRIGADR_WR0 

# instance INST95 
.subckt BUF IN0=RAM_A1 Z=TRIGADR_WR1 

# instance INST96 
.subckt BUF IN0=RAM_A2 Z=TRIGADR_WR2 

# instance INST97 
.subckt BUF IN0=RAM_A3 Z=TRIGADR_WR3 

# instance INST98 
.subckt BUF IN0=RAM_A4 Z=TRIGADR_WR4 

# instance INST99 
.subckt AND2B1 IN0=ACQ_BEGIN IN1=RUN Z=N160724 

# instance U51 
.subckt CNTB16DL D0=N131094 D1=SB_WD0 D2=SB_WD1 D3=SB_WD2 D4=SB_WD3 D5=SB_WD4 D6=SB_WD5 D7=SB_WD6 D8=SB_WD7 D9=SB_WD8 D10=SB_WD9 D11=SB_WD10 D12=SB_WD11 D13=N131094 D14=N131094 D15=N131094 LD=REG2_CS CLK=N182142 Q0=N133030 Q1=N133028 Q2=N133026 Q3=N133024 Q4=N133022 Q5=N133020 Q6=N133018 Q7=N133062 Q8=N133060 Q9=N133058 Q10=N139394 Q11=N139401 Q12=XPLA__dummy_o Q13=XPLA__dummy_o Q14=XPLA__dummy_o Q15=XPLA__dummy_o 

# instance U52 
.subckt GND O=N131094 

# instance U53 
.subckt VDD O=N177828 

# instance U54 
.subckt CNTB16URE CLK=SAMPL_CLK RST=ACQ_RESET CE=N160724 Q0=INPUT_HILO Q1=RAM_A0 Q2=RAM_A1 Q3=RAM_A2 Q4=RAM_A3 Q5=RAM_A4 Q6=RAM_A5 Q7=RAM_A6 Q8=RAM_A7 Q9=RAM_A8 Q10=RAM_A9 Q11=RAM_A10 Q12=RAM_A11 Q13=RAM_A12 Q14=XPLA__dummy_o Q15=XPLA__dummy_o 

# instance INST100 
.subckt BUF IN0=RAM_A5 Z=TRIGADR_WR5 

# instance INST101 
.subckt BUF IN0=RAM_A6 Z=TRIGADR_WR6 

# instance INST102 
.subckt BUF IN0=RAM_A7 Z=TRIGADR_WR7 

# instance INST103 
.subckt BUF IN0=RAM_A8 Z=TRIGADR_WR8 

# instance INST104 
.subckt BUF IN0=RAM_A9 Z=TRIGADR_WR9 

# instance INST105 
.subckt BUF IN0=RAM_A10 Z=TRIGADR_WR10 

# instance INST106 
.subckt BUF IN0=RAM_A11 Z=TRIGADR_WR11 

# instance INST107 
.subckt BUF IN0=RAM_A12 Z=TRIGADR_WR12 

# instance INST108 
.subckt BUF IN0=BANK0 Z=RAM_A13 

# instance INST109 
.subckt BUF IN0=BANK1 Z=RAM_A14 

# instance INST110 
.subckt BUF IN0=BANK2 Z=RAM_A15 

# instance INST111 
.subckt BUF IN0=BANK3 Z=RAM_A16 

# instance INST112 
.subckt BUF IN0=BANK4 Z=RAM_A17 

# instance INST80 
.subckt AND2 IN0=SAMPL_CLK IN1=GOT_TRIG.Q Z=N183049 

# instance INST81 
.subckt OR2 IN0=N183049 IN1=N182139 Z=N182142 

# instance INST82 
.subckt AND2 IN0=SP_WEn IN1=REG2_CS Z=N182139 

# instance INST83 
.subckt AND2B2 IN0=N139401 IN1=N139394 Z=N139441 

# instance INST84 
.subckt AND5B5 IN0=N133058 IN1=N133060 IN2=N133062 IN3=N133018 IN4=N133020 Z=N136978 

# instance INST85 
.subckt AND3 IN0=N139441 IN1=N136978 IN2=N139448 Z=CLR_RUN 

# instance INST86 
.subckt AND5B5 IN0=N133022 IN1=N133024 IN2=N133026 IN3=N133028 IN4=N133030 Z=N139448 

# instance INST87 
.subckt BUF IN0=SB_WD12 Z=XPLA__dummy_o 

# instance INST88 
.subckt BUF IN0=SB_WD13 Z=XPLA__dummy_o 

# instance INST89 
.subckt BUF IN0=SB_WD14 Z=XPLA__dummy_o 

# instance SAMPLE_CLK_GEN 
.subckt SAMPLE_CLK_GEN SYS_CLK=SYS_CLK RUN=RUN ACQ_RESET=ACQ_RESET CNT_DWN0=CNT_DWN0 CNT_DWN1=CNT_DWN1 CNT_DWN2=CNT_DWN2 CNT_DWN3=CNT_DWN3 CNT_DWN4=CNT_DWN4 CNT_DWN5=CNT_DWN5 CNT_DWN6=CNT_DWN6 CNT_DWN7=CNT_DWN7 CNT_DWN8=CNT_DWN8 CNT_DWN9=CNT_DWN9 CNT_DWN10=CNT_DWN10 CNT_DWN11=CNT_DWN11 CNT_DWN12=CNT_DWN12 SELCLK0=SELCLK0 SELCLK1=SELCLK1 SELCLK2=SELCLK2 SAMPL_CLK=SAMPL_CLK 

# instance ACQ_CNT1 
.subckt ACQ_CNT1 RUN=RUN SYS_CLK=SYS_CLK SAMPL_CLK=SAMPL_CLK ACQ_RESET=ACQ_RESET ACQ_BEGIN=ACQ_BEGIN 

# instance ACQ_DATA_CTL 
.subckt ACQ_DATA_CTL TRIGGER0=TRIGGER0 TRIGGER1=TRIGGER1 TRIGGER2=TRIGGER2 TRIGGER3=TRIGGER3 TRIGGER4=TRIGGER4 TRIGGER5=TRIGGER5 TRIGGER6=TRIGGER6 TRIGGER7=TRIGGER7 TRIGGER8=TRIGGER8 TRIGGER9=TRIGGER9 TRIGGER10=TRIGGER10 TRIGGER11=TRIGGER11 TRIGGER12=TRIGGER12 TRIGGER13=TRIGGER13 TRIGGER14=TRIGGER14 TRIGGER15=TRIGGER15 CH_IN0=CH_IN0 CH_IN1=CH_IN1 CH_IN2=CH_IN2 CH_IN3=CH_IN3 CH_IN4=CH_IN4 CH_IN5=CH_IN5 CH_IN6=CH_IN6 CH_IN7=CH_IN7 SP_OE=SP_OE INPUT_HILO=INPUT_HILO SAMPL_CLK=SAMPL_CLK ACQ_RESET=ACQ_RESET IN_STATUS0=IN_STATUS0 IN_STATUS1=IN_STATUS1 IN_STATUS2=IN_STATUS2 IN_STATUS3=IN_STATUS3 IN_STATUS4=IN_STATUS4 IN_STATUS5=IN_STATUS5 IN_STATUS6=IN_STATUS6 IN_STATUS7=IN_STATUS7 RAM_D0=RAM_D0 RAM_D1=RAM_D1 RAM_D2=RAM_D2 RAM_D3=RAM_D3 RAM_D4=RAM_D4 RAM_D5=RAM_D5 RAM_D6=RAM_D6 RAM_D7=RAM_D7 RAM_D8=RAM_D8 RAM_D9=RAM_D9 RAM_D10=RAM_D10 RAM_D11=RAM_D11 RAM_D12=RAM_D12 RAM_D13=RAM_D13 RAM_D14=RAM_D14 RAM_D15=RAM_D15 TRIGMATCH=N177842 

# instance INST93 of cell INV 
.names RUN STOP 
0 1 

.end 

#$ MODULE SB_R_DATA 
#$ PINS 49 REG_RD MEM_RD0 MEM_RD1 MEM_RD2 MEM_RD3 MEM_RD4 MEM_RD5 MEM_RD6 MEM_RD7 MEM_RD8 MEM_RD9 MEM_RD10 MEM_RD11 MEM_RD12 MEM_RD13 MEM_RD14 MEM_RD15 REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 SB_RD0 SB_RD1 SB_RD2 SB_RD3 SB_RD4 SB_RD5 SB_RD6 SB_RD7 SB_RD8 SB_RD9 SB_RD10 SB_RD11 SB_RD12 SB_RD13 SB_RD14 SB_RD15 
.model SB_R_DATA 
.inputs REG_RD MEM_RD0 MEM_RD1 MEM_RD2 MEM_RD3 MEM_RD4 MEM_RD5 MEM_RD6 MEM_RD7 MEM_RD8 MEM_RD9 MEM_RD10 MEM_RD11 MEM_RD12 MEM_RD13 MEM_RD14 MEM_RD15 REG_RD0 REG_RD1 REG_RD2 REG_RD3 REG_RD4 REG_RD5 REG_RD6 REG_RD7 REG_RD8 REG_RD9 REG_RD10 REG_RD11 REG_RD12 REG_RD13 REG_RD14 REG_RD15 
.outputs SB_RD0 SB_RD1 SB_RD2 SB_RD3 SB_RD4 SB_RD5 SB_RD6 SB_RD7 SB_RD8 SB_RD9 SB_RD10 SB_RD11 SB_RD12 SB_RD13 SB_RD14 SB_RD15 

# instance U13 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD8 IN1=REG_RD8 Z=SB_RD8 

# instance U14 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD9 IN1=REG_RD9 Z=SB_RD9 

# instance U15 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD10 IN1=REG_RD10 Z=SB_RD10 

# instance U16 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD11 IN1=REG_RD11 Z=SB_RD11 

# instance U17 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD12 IN1=REG_RD12 Z=SB_RD12 

# instance U18 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD13 IN1=REG_RD13 Z=SB_RD13 

# instance U19 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD14 IN1=REG_RD14 Z=SB_RD14 

# instance U20 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD15 IN1=REG_RD15 Z=SB_RD15 

# instance U5 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD0 IN1=REG_RD0 Z=SB_RD0 

# instance U6 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD1 IN1=REG_RD1 Z=SB_RD1 

# instance U7 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD2 IN1=REG_RD2 Z=SB_RD2 

# instance U8 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD3 IN1=REG_RD3 Z=SB_RD3 

# instance U9 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD4 IN1=REG_RD4 Z=SB_RD4 

# instance U10 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD5 IN1=REG_RD5 Z=SB_RD5 

# instance U11 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD6 IN1=REG_RD6 Z=SB_RD6 

# instance U12 
.subckt MUX21 SEL=REG_RD IN0=MEM_RD7 IN1=REG_RD7 Z=SB_RD7 

.end 

#$ MODULE RAM_W_DATA 
#$ PINS 49 SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 RUN MEM_WD0 MEM_WD1 MEM_WD2 MEM_WD3 MEM_WD4 MEM_WD5 MEM_WD6 MEM_WD7 MEM_WD8 MEM_WD9 MEM_WD10 MEM_WD11 MEM_WD12 MEM_WD13 MEM_WD14 MEM_WD15 
.model RAM_W_DATA 
.inputs SB_WD0 SB_WD1 SB_WD2 SB_WD3 SB_WD4 SB_WD5 SB_WD6 SB_WD7 SB_WD8 SB_WD9 SB_WD10 SB_WD11 SB_WD12 SB_WD13 SB_WD14 SB_WD15 RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 RUN 
.outputs MEM_WD0 MEM_WD1 MEM_WD2 MEM_WD3 MEM_WD4 MEM_WD5 MEM_WD6 MEM_WD7 MEM_WD8 MEM_WD9 MEM_WD10 MEM_WD11 MEM_WD12 MEM_WD13 MEM_WD14 MEM_WD15 

# instance U55 
.subckt MUX21 SEL=RUN IN0=SB_WD0 IN1=RAM_D0 Z=MEM_WD0 

# instance U56 
.subckt MUX21 SEL=RUN IN0=SB_WD1 IN1=RAM_D1 Z=MEM_WD1 

# instance U57 
.subckt MUX21 SEL=RUN IN0=SB_WD2 IN1=RAM_D2 Z=MEM_WD2 

# instance U58 
.subckt MUX21 SEL=RUN IN0=SB_WD3 IN1=RAM_D3 Z=MEM_WD3 

# instance U59 
.subckt MUX21 SEL=RUN IN0=SB_WD4 IN1=RAM_D4 Z=MEM_WD4 

# instance U60 
.subckt MUX21 SEL=RUN IN0=SB_WD5 IN1=RAM_D5 Z=MEM_WD5 

# instance U61 
.subckt MUX21 SEL=RUN IN0=SB_WD6 IN1=RAM_D6 Z=MEM_WD6 

# instance U62 
.subckt MUX21 SEL=RUN IN0=SB_WD7 IN1=RAM_D7 Z=MEM_WD7