analyzer.bl3

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

#$ LIBRARY ps 
#$ LIBRARY MAIN_LIB 
#$ MODULE LogicAnalyzer 
#$ PINS 104 SP_A21 SP_A10 SP_A4 SP_CS0n SP_A11 SP_A5 SP_A12 SP_A6 SP_A13 SP_A7 SP_A14 SP_A8 CH_IN0 SP_A15 SP_A9 CH_IN1 SP_A16 SYS_CLK CH_IN2 SP_A17 SP_OEn CH_IN3 SP_A18 CH_IN4 SP_A19 CH_IN5 CH_IN6 CH_IN7 SP_RESETn SP_A1 SP_A2 SP_WEn SP_A20 SP_A3 SP_CS1n D11 D3 SP_D7 A14 A0 D12 D4 SP_D8 A15 A1 D13 D5 SP_D9 A16 A2 D14 D6 SP_D10 OEn A17 A3 D15 D7 SP_D11 A18 A4 D8 SP_D12 RWn A19 A5 SRAM_LOW_BYTEn D9 SP_D13 A6 SRAM_UPPER_BYTEn SP_D14 A7 SP_D15 IO13 A8 IO14 A9 SP_D0 IO15 SP_D1 SP_IRQn LED_0 SP_D2 A20 LED_1 SP_D3 FLASH_CS0n A10 LED_2 RESET_MEMn D0 SP_D4 SRAM_CS1n A11 LED_3 D1 SP_D5 A12 FLASH_W_PROTECTn D10 D2 SP_D6 A13 
#$ NODES 140 STOP'co' N66744'co' SRAM_LOW_BYTEN'co' SP_WE'co' SP_CS0'co' SP_IRQ'co' REG_SEL'co' SP_CS1'co' REG_RD13'co' REG_RD12'co' REG_RD11'co' REG_RD10'co' REG_RD9'co' REG_RD8'co' REG_RD7'co' REG_RD6'co' REG_RD5'co' REG_RD4'co' REG_RD3'co' REG_RD2'co' REG_RD1'co' REG_RD0'co' CLR_RUN'co' ACQ_WRN'co' REG2_CS'co' SP_OE'co' GOT_TRIG'co' ACQ_RESET'co' INPUT_HILO'co' RUN'co' REG_RD15'co' REG_RD14'co' RAM_A11'co' RAM_A10'co' RAM_A9'co' RAM_A8'co' RAM_A7'co' RAM_A6'co' RAM_A5'co' RAM_A4'co' RAM_A3'co' RAM_A2'co' RAM_A1'co' RAM_A0'co' SB_WD9'co' SB_WD8'co' SB_WD7'co' SB_WD6'co' SB_WD5'co' SB_WD4'co' SB_WD3'co' SB_WD2'co' SB_WD1'co' SB_WD0'co' RAM_A17'co' RAM_A16'co' RAM_A15'co' RAM_A14'co' RAM_A13'co' RAM_A12'co' CNT_DWN6'co' CNT_DWN5'co' CNT_DWN4'co' CNT_DWN3'co' CNT_DWN2'co' CNT_DWN1'co' CNT_DWN0'co' SELCLK2'co' SELCLK1'co' SELCLK0'co' SB_WD15'co' SB_WD14'co' SB_WD13'co' SB_WD12'co' SB_WD11'co' SB_WD10'co' TRIGGER1'co' TRIGGER0'co' IN_STATUS7'co' IN_STATUS6'co' IN_STATUS5'co' IN_STATUS4'co' IN_STATUS3'co' IN_STATUS2'co' IN_STATUS1'co' IN_STATUS0'co' CNT_DWN12'co' CNT_DWN11'co' CNT_DWN10'co' CNT_DWN9'co' CNT_DWN8'co' CNT_DWN7'co' BANK1'co' BANK0'co' TRIGGER15'co' TRIGGER14'co' TRIGGER13'co' TRIGGER12'co' TRIGGER11'co' TRIGGER10'co' TRIGGER9'co' TRIGGER8'co' TRIGGER7'co' TRIGGER6'co' TRIGGER5'co' TRIGGER4'co' TRIGGER3'co' TRIGGER2'co' RAM_D12'co' RAM_D11'co' RAM_D10'co' RAM_D9'co' RAM_D8'co' RAM_D7'co' RAM_D6'co' RAM_D5'co' RAM_D4'co' RAM_D3'co' RAM_D2'co' RAM_D1'co' RAM_D0'co' BANK4'co' BANK3'co' BANK2'co' TRIGADR_WR12'co' TRIGADR_WR11'co' TRIGADR_WR10'co' TRIGADR_WR9'co' TRIGADR_WR8'co' TRIGADR_WR7'co' TRIGADR_WR6'co' TRIGADR_WR5'co' TRIGADR_WR4'co' TRIGADR_WR3'co' TRIGADR_WR2'co' TRIGADR_WR1'co' TRIGADR_WR0'co' RAM_D15'co' RAM_D14'co' RAM_D13'co' 
.model LogicAnalyzer 
.inputs SP_A21 SP_A10 SP_A4 SP_CS0n SP_A11 SP_A5 SP_A12 SP_A6 SP_A13 SP_A7 SP_A14 SP_A8 CH_IN0 SP_A15 SP_A9 CH_IN1 SP_A16 SYS_CLK CH_IN2 SP_A17 SP_OEn CH_IN3 SP_A18 CH_IN4 SP_A19 CH_IN5 CH_IN6 CH_IN7 SP_RESETn SP_A1 SP_A2 SP_WEn SP_A20 SP_A3 SP_CS1n 
.outputs D11 D3 SP_D7 A14 A0 D12 D4 SP_D8 A15 A1 D13 D5 SP_D9 A16 A2 D14 D6 SP_D10 OEn A17 A3 D15 D7 SP_D11 A18 A4 D8 SP_D12 RWn A19 A5 SRAM_LOW_BYTEn D9 SP_D13 A6 SRAM_UPPER_BYTEn SP_D14 A7 SP_D15 IO13 A8 IO14 A9 SP_D0 IO15 SP_D1 SP_IRQn LED_0 SP_D2 A20 LED_1 SP_D3 FLASH_CS0n A10 LED_2 RESET_MEMn D0 SP_D4 SRAM_CS1n A11 LED_3 D1 SP_D5 A12 FLASH_W_PROTECTn D10 D2 SP_D6 A13 

# instance U21 
.subckt MUX21 SEL=RUN IN0=SP_OEn IN1=N66744 Z=OEn 

# instance U22 
.subckt VDD O=N66744 

# instance U23 
.subckt MUX21 SEL=RUN IN0=SP_WEn IN1=ACQ_WRN Z=RWn 

# instance U24 
.subckt MUX21 SEL=RUN IN0=SP_CS1n IN1=STOP Z=SRAM_CS1n 

# instance U25 
.subckt VDD O=FLASH_W_PROTECTn 

# instance U26 
.subckt GND O=SRAM_LOW_BYTEN 

# instance U27 
.subckt GND O=SP_IRQ 

# instance INST41 
.subckt BUF IN0=SRAM_CS1n Z=IO15 

# instance INST42 
.subckt BUF IN0=RUN Z=IO14 

# instance INST43 
.subckt BUF IN0=GOT_TRIG Z=IO13 

# instance INST44 
.subckt BUF IN0=SP_RESETn Z=RESET_MEMn 

# instance INST45 
.subckt BUF IN0=SP_CS0n Z=FLASH_CS0n 

# instance DATA_BUS 
.subckt DATA_BUS SP_CS0=SP_CS0 SP_CS1=SP_CS1 SP_OE=SP_OE SP_WE=SP_WE RAM_D0=RAM_D0 RAM_D1=RAM_D1 RAM_D2=RAM_D2 RAM_D3=RAM_D3 RAM_D4=RAM_D4 RAM_D5=RAM_D5 RAM_D6=RAM_D6 RAM_D7=RAM_D7 RAM_D8=RAM_D8 RAM_D9=RAM_D9 RAM_D10=RAM_D10 RAM_D11=RAM_D11 RAM_D12=RAM_D12 RAM_D13=RAM_D13 RAM_D14=RAM_D14 RAM_D15=RAM_D15 REG_RD0=REG_RD0 REG_RD1=REG_RD1 REG_RD2=REG_RD2 REG_RD3=REG_RD3 REG_RD4=REG_RD4 REG_RD5=REG_RD5 REG_RD6=REG_RD6 REG_RD7=REG_RD7 REG_RD8=REG_RD8 REG_RD9=REG_RD9 REG_RD10=REG_RD10 REG_RD11=REG_RD11 REG_RD12=REG_RD12 REG_RD13=REG_RD13 REG_RD14=REG_RD14 REG_RD15=REG_RD15 RUN=RUN REG_SEL=REG_SEL SB_WD0=SB_WD0 SB_WD1=SB_WD1 SB_WD2=SB_WD2 SB_WD3=SB_WD3 SB_WD4=SB_WD4 SB_WD5=SB_WD5 SB_WD6=SB_WD6 SB_WD7=SB_WD7 SB_WD8=SB_WD8 SB_WD9=SB_WD9 SB_WD10=SB_WD10 SB_WD11=SB_WD11 SB_WD12=SB_WD12 SB_WD13=SB_WD13 SB_WD14=SB_WD14 SB_WD15=SB_WD15 SP_D0=SP_D0 SP_D1=SP_D1 SP_D2=SP_D2 SP_D3=SP_D3 SP_D4=SP_D4 SP_D5=SP_D5 SP_D6=SP_D6 SP_D7=SP_D7 SP_D8=SP_D8 SP_D9=SP_D9 SP_D10=SP_D10 SP_D11=SP_D11 SP_D12=SP_D12 SP_D13=SP_D13 SP_D14=SP_D14 SP_D15=SP_D15 D0=D0 D1=D1 D2=D2 D3=D3 D4=D4 D5=D5 D6=D6 D7=D7 D8=D8 D9=D9 D10=D10 D11=D11 D12=D12 D13=D13 D14=D14 D15=D15 

# instance ADDRESS_BUS 
.subckt ADDRESS_BUS RAM_A0=RAM_A0 RAM_A1=RAM_A1 RAM_A2=RAM_A2 RAM_A3=RAM_A3 RAM_A4=RAM_A4 RAM_A5=RAM_A5 RAM_A6=RAM_A6 RAM_A7=RAM_A7 RAM_A8=RAM_A8 RAM_A9=RAM_A9 RAM_A10=RAM_A10 RAM_A11=RAM_A11 RAM_A12=RAM_A12 RAM_A13=RAM_A13 RAM_A14=RAM_A14 RAM_A15=RAM_A15 RAM_A16=RAM_A16 RAM_A17=RAM_A17 RUN=RUN SP_A1=SP_A1 SP_A2=SP_A2 SP_A3=SP_A3 SP_A4=SP_A4 SP_A5=SP_A5 SP_A6=SP_A6 SP_A7=SP_A7 SP_A8=SP_A8 SP_A9=SP_A9 SP_A10=SP_A10 SP_A11=SP_A11 SP_A12=SP_A12 SP_A13=SP_A13 SP_A14=SP_A14 SP_A15=SP_A15 SP_A16=SP_A16 SP_A17=SP_A17 SP_A18=SP_A18 SP_A19=SP_A19 SP_A20=SP_A20 SP_A21=SP_A21 A0=A0 A1=A1 A2=A2 A3=A3 A4=A4 A5=A5 A6=A6 A7=A7 A8=A8 A9=A9 A10=A10 A11=A11 A12=A12 A13=A13 A14=A14 A15=A15 A16=A16 A17=A17 A18=A18 A19=A19 A20=A20 

# instance ACQ_CONTROL 
.subckt ACQ_CONTROL BANK0=BANK0 BANK1=BANK1 BANK2=BANK2 BANK3=BANK3 BANK4=BANK4 TRIGGER0=TRIGGER0 TRIGGER1=TRIGGER1 TRIGGER2=TRIGGER2 TRIGGER3=TRIGGER3 TRIGGER4=TRIGGER4 TRIGGER5=TRIGGER5 TRIGGER6=TRIGGER6 TRIGGER7=TRIGGER7 TRIGGER8=TRIGGER8 TRIGGER9=TRIGGER9 TRIGGER10=TRIGGER10 TRIGGER11=TRIGGER11 TRIGGER12=TRIGGER12 TRIGGER13=TRIGGER13 TRIGGER14=TRIGGER14 TRIGGER15=TRIGGER15 RUN=RUN CH_IN0=CH_IN0 CH_IN1=CH_IN1 CH_IN2=CH_IN2 CH_IN3=CH_IN3 CH_IN4=CH_IN4 CH_IN5=CH_IN5 CH_IN6=CH_IN6 CH_IN7=CH_IN7 SYS_CLK=SYS_CLK CNT_DWN0=CNT_DWN0 CNT_DWN1=CNT_DWN1 CNT_DWN2=CNT_DWN2 CNT_DWN3=CNT_DWN3 CNT_DWN4=CNT_DWN4 CNT_DWN5=CNT_DWN5 CNT_DWN6=CNT_DWN6 CNT_DWN7=CNT_DWN7 CNT_DWN8=CNT_DWN8 CNT_DWN9=CNT_DWN9 CNT_DWN10=CNT_DWN10 CNT_DWN11=CNT_DWN11 CNT_DWN12=CNT_DWN12 SELCLK0=SELCLK0 SELCLK1=SELCLK1 SELCLK2=SELCLK2 SP_OE=SP_OE REG2_CS=REG2_CS SP_WEn=SP_WEn SB_WD0=SB_WD0 SB_WD1=SB_WD1 SB_WD2=SB_WD2 SB_WD3=SB_WD3 SB_WD4=SB_WD4 SB_WD5=SB_WD5 SB_WD6=SB_WD6 SB_WD7=SB_WD7 SB_WD8=SB_WD8 SB_WD9=SB_WD9 SB_WD10=SB_WD10 SB_WD11=SB_WD11 SB_WD12=SB_WD12 SB_WD13=SB_WD13 SB_WD14=SB_WD14 SB_WD15=SB_WD15 ACQ_RESET=ACQ_RESET INPUT_HILO=INPUT_HILO GOT_TRIG=GOT_TRIG IN_STATUS0=IN_STATUS0 IN_STATUS1=IN_STATUS1 IN_STATUS2=IN_STATUS2 IN_STATUS3=IN_STATUS3 IN_STATUS4=IN_STATUS4 IN_STATUS5=IN_STATUS5 IN_STATUS6=IN_STATUS6 IN_STATUS7=IN_STATUS7 RAM_D0=RAM_D0 RAM_D1=RAM_D1 RAM_D2=RAM_D2 RAM_D3=RAM_D3 RAM_D4=RAM_D4 RAM_D5=RAM_D5 RAM_D6=RAM_D6 RAM_D7=RAM_D7 RAM_D8=RAM_D8 RAM_D9=RAM_D9 RAM_D10=RAM_D10 RAM_D11=RAM_D11 RAM_D12=RAM_D12 RAM_D13=RAM_D13 RAM_D14=RAM_D14 RAM_D15=RAM_D15 TRIGADR_WR0=TRIGADR_WR0 TRIGADR_WR1=TRIGADR_WR1 TRIGADR_WR2=TRIGADR_WR2 TRIGADR_WR3=TRIGADR_WR3 TRIGADR_WR4=TRIGADR_WR4 TRIGADR_WR5=TRIGADR_WR5 TRIGADR_WR6=TRIGADR_WR6 TRIGADR_WR7=TRIGADR_WR7 TRIGADR_WR8=TRIGADR_WR8 TRIGADR_WR9=TRIGADR_WR9 TRIGADR_WR10=TRIGADR_WR10 TRIGADR_WR11=TRIGADR_WR11 TRIGADR_WR12=TRIGADR_WR12 RAM_A0=RAM_A0 RAM_A1=RAM_A1 RAM_A2=RAM_A2 RAM_A3=RAM_A3 RAM_A4=RAM_A4 RAM_A5=RAM_A5 RAM_A6=RAM_A6 RAM_A7=RAM_A7 RAM_A8=RAM_A8 RAM_A9=RAM_A9 RAM_A10=RAM_A10 RAM_A11=RAM_A11 RAM_A12=RAM_A12 RAM_A13=RAM_A13 RAM_A14=RAM_A14 RAM_A15=RAM_A15 RAM_A16=RAM_A16 RAM_A17=RAM_A17 CLR_RUN=CLR_RUN ACQ_WRn=ACQ_WRN 

# instance REGISTERS 
.subckt REGISTERS SP_A19=SP_A19 SP_CS1=SP_CS1 SP_A1=SP_A1 SP_A2=SP_A2 SP_A3=SP_A3 SP_A4=SP_A4 SB_WD0=SB_WD0 SB_WD1=SB_WD1 SB_WD2=SB_WD2 SB_WD3=SB_WD3 SB_WD4=SB_WD4 SB_WD5=SB_WD5 SB_WD6=SB_WD6 SB_WD7=SB_WD7 SB_WD8=SB_WD8 SB_WD9=SB_WD9 SB_WD10=SB_WD10 SB_WD11=SB_WD11 SB_WD12=SB_WD12 SB_WD13=SB_WD13 SB_WD14=SB_WD14 SB_WD15=SB_WD15 IN_STATUS0=IN_STATUS0 IN_STATUS1=IN_STATUS1 IN_STATUS2=IN_STATUS2 IN_STATUS3=IN_STATUS3 IN_STATUS4=IN_STATUS4 IN_STATUS5=IN_STATUS5 IN_STATUS6=IN_STATUS6 IN_STATUS7=IN_STATUS7 SP_WEn=SP_WEn CLR_RUN=CLR_RUN TRIGADR_WR0=TRIGADR_WR0 TRIGADR_WR1=TRIGADR_WR1 TRIGADR_WR2=TRIGADR_WR2 TRIGADR_WR3=TRIGADR_WR3 TRIGADR_WR4=TRIGADR_WR4 TRIGADR_WR5=TRIGADR_WR5 TRIGADR_WR6=TRIGADR_WR6 TRIGADR_WR7=TRIGADR_WR7 TRIGADR_WR8=TRIGADR_WR8 TRIGADR_WR9=TRIGADR_WR9 TRIGADR_WR10=TRIGADR_WR10 TRIGADR_WR11=TRIGADR_WR11 TRIGADR_WR12=TRIGADR_WR12 INPUT_HILO=INPUT_HILO GOT_TRIG=GOT_TRIG ACQ_RESET=ACQ_RESET REG_SEL=REG_SEL REG_RD0=REG_RD0 REG_RD1=REG_RD1 REG_RD2=REG_RD2 REG_RD3=REG_RD3 REG_RD4=REG_RD4 REG_RD5=REG_RD5 REG_RD6=REG_RD6 REG_RD7=REG_RD7 REG_RD8=REG_RD8 REG_RD9=REG_RD9 REG_RD10=REG_RD10 REG_RD11=REG_RD11 REG_RD12=REG_RD12 REG_RD13=REG_RD13 REG_RD14=REG_RD14 REG_RD15=REG_RD15 TRIGGER0=TRIGGER0 TRIGGER1=TRIGGER1 TRIGGER2=TRIGGER2 TRIGGER3=TRIGGER3 TRIGGER4=TRIGGER4 TRIGGER5=TRIGGER5 TRIGGER6=TRIGGER6 TRIGGER7=TRIGGER7 TRIGGER8=TRIGGER8 TRIGGER9=TRIGGER9 TRIGGER10=TRIGGER10 TRIGGER11=TRIGGER11 TRIGGER12=TRIGGER12 TRIGGER13=TRIGGER13 TRIGGER14=TRIGGER14 TRIGGER15=TRIGGER15 LED_0=LED_0 LED_1=LED_1 LED_2=LED_2 LED_3=LED_3 CNT_DWN0=CNT_DWN0 CNT_DWN1=CNT_DWN1 CNT_DWN2=CNT_DWN2 CNT_DWN3=CNT_DWN3 CNT_DWN4=CNT_DWN4 CNT_DWN5=CNT_DWN5 CNT_DWN6=CNT_DWN6 CNT_DWN7=CNT_DWN7 CNT_DWN8=CNT_DWN8 CNT_DWN9=CNT_DWN9 CNT_DWN10=CNT_DWN10 CNT_DWN11=CNT_DWN11 CNT_DWN12=CNT_DWN12 SELCLK0=SELCLK0 SELCLK1=SELCLK1 SELCLK2=SELCLK2 RUN=RUN BANK0=BANK0 BANK1=BANK1 BANK2=BANK2 BANK3=BANK3 BANK4=BANK4 REG2_CS=REG2_CS 

# instance INST46 of cell INV 
.names SP_IRQ SP_IRQn 
0 1 

# instance INST47 of cell INV 
.names SP_OEn SP_OE 
0 1 

# instance INST48 of cell INV 
.names RUN STOP 
0 1 

# instance INST49 of cell INV 
.names SP_WEn SP_WE 
0 1 

# instance INST50 of cell INV 
.names SP_CS0n SP_CS0 
0 1 

# instance INST51 of cell INV 
.names SP_CS1n SP_CS1 
0 1 

.names SRAM_LOW_BYTEN SRAM_LOW_BYTEn
1 1

.names SRAM_LOW_BYTEN SRAM_UPPER_BYTEn
1 1

.end 

#$ MODULE ACQ_CNT1 
#$ PINS 5 RUN SYS_CLK SAMPL_CLK ACQ_RESET ACQ_BEGIN 
#$ NODES 6 N95948'co' QA'co' N72307'co' N71237'co' N71119'co' XPLA__dummy_o'co' 
.model ACQ_CNT1 
.inputs RUN SYS_CLK SAMPL_CLK QA.Q 
.outputs ACQ_RESET ACQ_BEGIN 

# instance INST113 
.subckt DFFR D=N71237 CLK=SYS_CLK RST=N71119 Q=QA QN=XPLA__dummy_o 

# instance INST114 
.subckt DFFR D=QA.Q CLK=SYS_CLK RST=N71119 Q=XPLA__dummy_o QN=N72307 

# instance INST115 
.subckt AND2 IN0=N72307 IN1=RUN Z=ACQ_RESET 

# instance INST117 
.subckt DFFR D=N95948 CLK=ACQ_RESET RST=SAMPL_CLK Q=ACQ_BEGIN QN=XPLA__dummy_o 

# instance U71 
.subckt VDD O=N71237 

# instance U72 
.subckt VDD O=N95948 

# instance INST116 of cell INV 
.names RUN N71119 
0 1 

.end 

#$ MODULE ACQ_DATA_CTL 
#$ PINS 53 TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 CH_IN0 CH_IN1 CH_IN2 CH_IN3 CH_IN4 CH_IN5 CH_IN6 CH_IN7 SP_OE INPUT_HILO SAMPL_CLK ACQ_RESET IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 TRIGMATCH 
#$ NODES 35 N136464'co' N136524'co' T5'co' N136428'co' N135837'co' T1'co' N136247'co' N136283'co' N136440'co' T0'co' T6'co' T3'co' N136476'co' N136271'co' N136516'co' N135849'co' N135510'co' N136235'co' N135532'co' T2'co' N136512'co' T7'co' N136500'co' T4'co' IN3'co' IN2'co' IN4'co' IN5'co' IN6'co' IN7'co' IN0'co' IN1'co' N161559'co' N128544'co' N161259'co' 
.model ACQ_DATA_CTL 
.inputs TRIGGER0 TRIGGER1 TRIGGER2 TRIGGER3 TRIGGER4 TRIGGER5 TRIGGER6 TRIGGER7 TRIGGER8 TRIGGER9 TRIGGER10 TRIGGER11 TRIGGER12 TRIGGER13 TRIGGER14 TRIGGER15 CH_IN0 CH_IN1 CH_IN2 CH_IN3 CH_IN4 CH_IN5 CH_IN6 CH_IN7 SP_OE INPUT_HILO SAMPL_CLK ACQ_RESET 
.outputs IN_STATUS0 IN_STATUS1 IN_STATUS2 IN_STATUS3 IN_STATUS4 IN_STATUS5 IN_STATUS6 IN_STATUS7 RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 TRIGMATCH 

# instance U120 
.subckt VDD O=N136516 

# instance U100 
.subckt GND O=N135510 

# instance U101 
.subckt GND O=N136235 

# instance U102 
.subckt GND O=N136428 

# instance U103 
.subckt MUX41 SEL0=TRIGGER2 SEL1=TRIGGER3 IN0=N136524 IN1=IN1 IN2=IN1 IN3=N136500 Z=T1 

# instance U104 
.subckt VDD O=N135532 

# instance U105 
.subckt GND O=N136524 

# instance U106 
.subckt VDD O=N136247 

# instance U107 
.subckt VDD O=N136440 

# instance U108 
.subckt VDD O=N136500 

# instance U109 
.subckt MUX41 SEL0=TRIGGER12 SEL1=TRIGGER13 IN0=N135837 IN1=IN6 IN2=IN6 IN3=N135849 Z=T6 

# instance U91 
.subckt REG8E D0=CH_IN0 D1=CH_IN1 D2=CH_IN2 D3=CH_IN3 D4=CH_IN4 D5=CH_IN5 D6=CH_IN6 D7=CH_IN7 CLK=N128544 CE=N161259 Q0=RAM_D0 Q1=RAM_D1 Q2=RAM_D2 Q3=RAM_D3 Q4=RAM_D4 Q5=RAM_D5 Q6=RAM_D6 Q7=RAM_D7 

# instance U92 
.subckt REG8E D0=CH_IN0 D1=CH_IN1 D2=CH_IN2 D3=CH_IN3 D4=CH_IN4 D5=CH_IN5 D6=CH_IN6 D7=CH_IN7 CLK=N128544 CE=N161559 Q0=RAM_D8 Q1=RAM_D9 Q2=RAM_D10 Q3=RAM_D11 Q4=RAM_D12 Q5=RAM_D13 Q6=RAM_D14 Q7=RAM_D15 

# instance U93 
.subckt VDD O=N161559 

# instance U94 
.subckt REG8 D0=CH_IN0 D1=CH_IN1 D2=CH_IN2 D3=CH_IN3 D4=CH_IN4 D5=CH_IN5 D6=CH_IN6 D7=CH_IN7 CLK=SP_OE Q0=IN_STATUS0 Q1=IN_STATUS1 Q2=IN_STATUS2 Q3=IN_STATUS3 Q4=IN_STATUS4 Q5=IN_STATUS5 Q6=IN_STATUS6 Q7=IN_STATUS7 

# instance U95 
.subckt BUF8 IN0=RAM_D15 IN1=RAM_D14 IN2=RAM_D13 IN3=RAM_D12 IN4=RAM_D11 IN5=RAM_D10 IN6=RAM_D9 IN7=RAM_D8 Z0=IN7 Z1=IN6 Z2=IN5 Z3=IN4 Z4=IN3 Z5=IN2 Z6=IN1 Z7=IN0 

# instance U96 
.subckt COMP8 A0=T0 A1=T1 A2=T2 A3=T3 A4=T4 A5=T5 A6=T6 A7=T7 B0=IN0 B1=IN1 B2=IN2 B3=IN3 B4=IN4 B5=IN5 B6=IN6 B7=IN7 EQ=TRIGMATCH 

# instance U97 
.subckt MUX41 SEL0=TRIGGER14 SEL1=TRIGGER15 IN0=N135510 IN1=IN7 IN2=IN7 IN3=N135532 Z=T7 

# instance U98 
.subckt MUX41 SEL0=TRIGGER10 SEL1=TRIGGER11 IN0=N136235 IN1=IN5 IN2=IN5 IN3=N136247 Z=T5 

# instance INST142 
.subckt OR2 IN0=ACQ_RESET IN1=SAMPL_CLK Z=N128544 

# instance U99 
.subckt MUX41 SEL0=TRIGGER6 SEL1=TRIGGER7 IN0=N136428 IN1=IN3 IN2=IN3 IN3=N136440 Z=T3 

# instance U110 
.subckt MUX41 SEL0=TRIGGER8 SEL1=TRIGGER9 IN0=N136271 IN1=IN4 IN2=IN4 IN3=N136283 Z=T4 

# instance U111 
.subckt MUX41 SEL0=TRIGGER4 SEL1=TRIGGER5 IN0=N136464 IN1=IN2 IN2=IN2 IN3=N136476 Z=T2 

# instance U112 
.subckt GND O=N135837 

# instance U113 
.subckt GND O=N136271 

# instance U114 
.subckt GND O=N136464 

# instance U115 
.subckt MUX41 SEL0=TRIGGER0 SEL1=TRIGGER1 IN0=N136512 IN1=IN0 IN2=IN0 IN3=N136516 Z=T0 

# instance U116 
.subckt GND O=N136512 

# instance U117 
.subckt VDD O=N135849 

# instance U118 
.subckt VDD O=N136283 

# instance U119 
.subckt VDD O=N136476 

# instance INST143 of cell INV 
.names INPUT_HILO N161259 
0 1 

.end 

#$ MODULE SAMPLE_CLK_GEN 
#$ PINS 20 SYS_CLK RUN ACQ_RESET CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 SAMPL_CLK 
#$ NODES 32 N133409'co' SYS_CLK4'co' N133052'co' N133028'co' N133054'co' SYS_CLK2'co' N133079'co' DWN_CLK'co' N133234'co' N133058'co' N133030'co' N136442'co' N133026'co' DWN_OUT'co' N133212'co' N125990'co' N133020'co' N125972'co' N133060'co' N133022'co' N133018'co' N133062'co' N133215'co' N133441'co' N133056'co' N133024'co' N124061'co' N133197'co' N1331745'co' XPLANOT__SYS_CLK4'co' XPLANOT__SYS_CLK2'co' XPLA__dummy_o'co' 
.model SAMPLE_CLK_GEN 
.inputs SYS_CLK RUN ACQ_RESET CNT_DWN0 CNT_DWN1 CNT_DWN2 CNT_DWN3 CNT_DWN4 CNT_DWN5 CNT_DWN6 CNT_DWN7 CNT_DWN8 CNT_DWN9 CNT_DWN10 CNT_DWN11 CNT_DWN12 SELCLK0 SELCLK1 SELCLK2 SYS_CLK4.Q SYS_CLK2.Q DWN_OUT.Q 
.outputs SAMPL_CLK 

# instance U46 
.subckt MUX41 SEL0=SELCLK0 SEL1=SELCLK1 IN0=SYS_CLK IN1=SYS_CLK2.Q IN2=SYS_CLK4.Q IN3=N124061 Z=DWN_CLK 

# instance U47 
.subckt MUX21 SEL=SELCLK2 IN0=DWN_CLK IN1=DWN_OUT.Q Z=SAMPL_CLK 

# instance U48 
.subckt GND O=N124061 

# instance U49 
.subckt CNTB16DLRE D0=CNT_DWN0 D1=CNT_DWN1 D2=CNT_DWN2 D3=CNT_DWN3 D4=CNT_DWN4 D5=CNT_DWN5 D6=CNT_DWN6 D7=CNT_DWN7 D8=CNT_DWN8 D9=CNT_DWN9 D10=CNT_DWN10 D11=CNT_DWN11 D12=CNT_DWN12 D13=N133079 D14=N133079 D15=N133079 LD=DWN_OUT.Q CE=N136442 CLK=DWN_CLK RST=ACQ_RESET Q0=N133030 Q1=N133028 Q2=N133026 Q3=N133024 Q4=N133022 Q5=N133020 Q6=N133018 Q7=N133062 Q8=N133060 Q9=N133058 Q10=N133056 Q11=N133054 Q12=N133052 Q13=N133234 Q14=N133197 Q15=XPLA__dummy_o 

# instance U50 
.subckt GND O=N133079 

# instance INST71