logicanalyzer.xrf

可编程器件厂商Xilinx的手持式逻辑分析仪的逻辑设计

Signal Name Cross Reference File

XPLA Designer Version 3.43

Design 'LogicAnalyzer' 


 LEGEND:  '>'  Functional Block Port Separator
          '/'  Hierarchy Path Separator
          '@'  Automatically Generated Node


Short Name                              Hierarchical Name
----------                              -----------------
D_0_                                    REGISTERS/                              
C_0_                                    ACQ_CONTROL/SAMPLE_CLK_GEN/             
A_0_                                    ACQ_CONTROL/ACQ_CNT1/                   
E_0_                                    REGISTERS/WREG6/                        
B_0_                                    ACQ_CONTROL/