📄 analyzer.ph1
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" XPLAOPT Version 3.43
" Created on Mon Aug 13 22:40:06 2001
" 207 Mcells, 2 FbNand, 396 PLApts, 4 Levels
" XPLAOPT -dev xcr3256xl-10cs280 -mode 1 -th 18 -fi 26 -xor n -reg -ucf
" c:\dad'sstuff\visor\logicanalyzer\analyzer\analyzer.ucf -it blif -i analyzer.bl3 -ot blif -o analyzer.blx -run s -log
" analyzer.er2 -ctrl analyzer.ctrl
MODULE LogicAnalyzer
A0 pin T5 ; " 2 pt.
A1 pin W10 ; " 2 pt.
A10 pin V5 ; " 2 pt.
A11 pin W5 ; " 2 pt.
A12 pin W4 ; " 2 pt.
A13 pin W3 ; " 2 pt.
A14 pin U6 ; " 2 pt.
A15 pin T6 ; " 2 pt.
A16 pin R6 ; " 2 pt.
A17 pin W7 ; " 2 pt.
A18 pin G1 ; " 1 pt.
A19 pin U5 ; " 1 pt.
A2 pin T9 ; " 2 pt.
A20 pin U4 ; " 1 pt.
A3 pin U9 ; " 2 pt.
A4 pin T8 ; " 2 pt.
A5 pin V7 ; " 2 pt.
A6 pin U7 ; " 2 pt.
A7 pin T7 ; " 2 pt.
A8 pin V6 ; " 2 pt.
A9 pin W6 ; " 2 pt.
CH_IN0 pin B1 ;
CH_IN1 pin C3 ;
CH_IN2 pin A4 ;
CH_IN3 pin B5 ;
CH_IN4 pin C5 ;
CH_IN5 pin A5 ;
CH_IN6 pin E6 ;
CH_IN7 pin D6 ;
D0 pin A14 ; " 2 pt.
D1 pin B13 ; " 2 pt.
D10 pin B12 ; " 2 pt.
D11 pin D10 ; " 2 pt.
D12 pin C9 ; " 2 pt.
D13 pin B8 ; " 2 pt.
D14 pin C7 ; " 2 pt.
D15 pin B7 ; " 2 pt.
D2 pin D12 ; " 2 pt.
D3 pin A12 ; " 2 pt.
D4 pin C10 ; " 2 pt.
D5 pin C8 ; " 2 pt.
D6 pin D7 ; " 2 pt.
D7 pin A7 ; " 2 pt.
D8 pin C13 ; " 2 pt.
D9 pin A13 ; " 2 pt.
FLASH_CS0n pin E14 ; " 1 pt.
FLASH_W_PROTECTn pin H2 ; " 1 pt.
IO13 pin E2 ; " 1 pt.
IO14 pin E4 ; " 2 pt.
IO15 pin E1 ; " 1 pt.
LED_0 pin F5 ; " 1 pt.
LED_1 pin F3 ; " 1 pt.
LED_2 pin F4 ; " 1 pt.
LED_3 pin G3 ; " 1 pt.
OEn pin D14 ; " 1 pt.
RESET_MEMn pin T13 ; " 1 pt.
RWn pin J2 ; " 2 pt.
SP_A1 pin T17 ;
SP_A10 pin F17 ;
SP_A11 pin H17 ;
SP_A12 pin M18 ;
SP_A13 pin L17 ;
SP_A14 pin E18 ;
SP_A15 pin K18 ;
SP_A16 pin H19 ;
SP_A17 pin L16 ;
SP_A18 pin M17 ;
SP_A19 pin E19 ;
SP_A2 pin R16 ;
SP_A20 pin F19 ;
SP_A21 pin H18 ;
SP_A3 pin R17 ;
SP_A4 pin N16 ;
SP_A5 pin M16 ;
SP_A6 pin R19 ;
SP_A7 pin N18 ;
SP_A8 pin K17 ;
SP_A9 pin J17 ;
SP_CS0n pin B19 ;
SP_CS1n pin G16 ;
SP_D0 pin V16 ; " 3 pt.
SP_D1 pin W15 ; " 3 pt.
SP_D10 pin U15 ; " 2 pt.
SP_D11 pin C16 ; " 2 pt.
SP_D12 pin A16 ; " 2 pt.
SP_D13 pin B17 ; " 2 pt.
SP_D14 pin B18 ; " 2 pt.
SP_D15 pin F15 ; " 2 pt.
SP_D2 pin T15 ; " 3 pt.
SP_D3 pin D15 ; " 3 pt.
SP_D4 pin E15 ; " 3 pt.
SP_D5 pin A15 ; " 3 pt.
SP_D6 pin A17 ; " 3 pt.
SP_D7 pin A18 ; " 3 pt.
SP_D8 pin V15 ; " 2 pt.
SP_D9 pin T16 ; " 2 pt.
SP_IRQn pin G19 ; " 1 pt.
SP_OEn pin G17 ;
SP_RESETn pin N17 ;
SP_WEn pin F18 ;
SRAM_CS1n pin K2 ; " 1 pt.
SRAM_LOW_BYTEn pin K3 ; " 0 pt.
SRAM_UPPER_BYTEn pin J3 ; " 0 pt.
SYS_CLK pin A10 ;
A_0_QA node ; " 1 pt.
A_0_xpla_dummy_o_1 node ; " 1 pt.
B_0_ACQ_BEGIN node ; " 1 pt.
B_0_N133018 node ; " 3 pt.
B_0_N133020 node ; " 3 pt.
B_0_N133022 node ; " 3 pt.
B_0_N133024 node ; " 3 pt.
B_0_N133026 node ; " 3 pt.
B_0_N133028 node ; " 3 pt.
B_0_N133030 node ; " 1 pt.
B_0_N133058 node ; " 3 pt.
B_0_N133060 node ; " 3 pt.
B_0_N133062 node ; " 3 pt.
B_0_N139394 node ; " 3 pt.
B_0_N139401 node ; " 3 pt.
B_0_N177842 node istype 'collapse'; " 16 pt.
B_0_SAMPL_CLK node istype 'collapse'; " 2 pt.
B_0_xpla_dummy_o_10 node ; " 2 pt.
B_0_xpla_dummy_o_11 node ; " 1 pt.
B_0_xpla_dummy_o_7 node ; " 3 pt.
B_0_xpla_dummy_o_8 node ; " 2 pt.
B_0_xpla_dummy_o_9 node ; " 2 pt.
BANK0 node istype 'collapse'; " 2 pt.
BANK1 node istype 'collapse'; " 2 pt.
BANK2 node istype 'collapse'; " 2 pt.
BANK3 node istype 'collapse'; " 2 pt.
BANK4 node istype 'collapse'; " 2 pt.
C_0_DWN_CLK node istype 'collapse'; " 3 pt.
C_0_DWN_OUT node ; " 3 pt.
C_0_N133018 node ; " 3 pt.
C_0_N133020 node ; " 3 pt.
C_0_N133022 node ; " 3 pt.
C_0_N133024 node ; " 3 pt.
C_0_N133026 node ; " 3 pt.
C_0_N133028 node ; " 3 pt.
C_0_N133030 node ; " 3 pt.
C_0_N133052 node ; " 3 pt.
C_0_N133054 node ; " 3 pt.
C_0_N133056 node ; " 3 pt.
C_0_N133058 node ; " 3 pt.
C_0_N133060 node ; " 3 pt.
C_0_N133062 node ; " 3 pt.
C_0_N133197 node ; " 2 pt.
C_0_N133234 node ; " 2 pt.
C_0_SYS_CLK2 node ; " 1 pt.
C_0_SYS_CLK4 node ; " 1 pt.
C_0_xpla_dummy_o_3 node ; " 2 pt.
CNT_DWN0 node istype 'collapse'; " 2 pt.
CNT_DWN1 node istype 'collapse'; " 2 pt.
CNT_DWN10 node istype 'collapse'; " 2 pt.
CNT_DWN11 node istype 'collapse'; " 2 pt.
CNT_DWN12 node istype 'collapse'; " 2 pt.
CNT_DWN2 node istype 'collapse'; " 2 pt.
CNT_DWN3 node istype 'collapse'; " 2 pt.
CNT_DWN4 node istype 'collapse'; " 2 pt.
CNT_DWN5 node istype 'collapse'; " 2 pt.
CNT_DWN6 node istype 'collapse'; " 2 pt.
CNT_DWN7 node istype 'collapse'; " 2 pt.
CNT_DWN8 node istype 'collapse'; " 2 pt.
CNT_DWN9 node istype 'collapse'; " 2 pt.
D_0_TRIG_HILO node ; " 1 pt.
D_0_TRIGADR_RD0 node ; " 1 pt.
D_0_TRIGADR_RD1 node ; " 1 pt.
D_0_TRIGADR_RD10 node ; " 1 pt.
D_0_TRIGADR_RD11 node ; " 1 pt.
D_0_TRIGADR_RD12 node ; " 1 pt.
D_0_TRIGADR_RD2 node ; " 1 pt.
D_0_TRIGADR_RD3 node ; " 1 pt.
D_0_TRIGADR_RD4 node ; " 1 pt.
D_0_TRIGADR_RD5 node ; " 1 pt.
D_0_TRIGADR_RD6 node ; " 1 pt.
D_0_TRIGADR_RD7 node ; " 1 pt.
D_0_TRIGADR_RD8 node ; " 1 pt.
D_0_TRIGADR_RD9 node ; " 1 pt.
E_0_xpla_dummy_o_64 node ; " 2 pt.
E_0_xpla_dummy_o_66 node ; " 2 pt.
E_0_xpla_dummy_o_68 node ; " 2 pt.
IN_STATUS0 node istype 'collapse'; " 1 pt.
IN_STATUS1 node istype 'collapse'; " 1 pt.
IN_STATUS2 node istype 'collapse'; " 1 pt.
IN_STATUS3 node istype 'collapse'; " 1 pt.
IN_STATUS4 node istype 'collapse'; " 1 pt.
IN_STATUS5 node istype 'collapse'; " 1 pt.
IN_STATUS6 node istype 'collapse'; " 1 pt.
IN_STATUS7 node istype 'collapse'; " 1 pt.
INPUT_HILO node istype 'collapse'; " 1 pt.
N_PZ_5586 node istype 'keep'; " 1 pt.
N_PZ_5587 node istype 'keep'; " 1 pt.
N_PZ_5595 node istype 'collapse'; " 3 pt.
N_PZ_5596 node istype 'collapse'; " 2 pt.
N_PZ_5597 node istype 'collapse'; " 2 pt.
N_PZ_5599 node istype 'collapse'; " 2 pt.
RAM_A0 node istype 'collapse'; " 1 pt.
RAM_A1 node istype 'collapse'; " 1 pt.
RAM_A10 node istype 'collapse'; " 1 pt.
RAM_A11 node istype 'collapse'; " 1 pt.
RAM_A12 node istype 'collapse'; " 1 pt.
RAM_A2 node istype 'collapse'; " 1 pt.
RAM_A3 node istype 'collapse'; " 1 pt.
RAM_A4 node istype 'collapse'; " 1 pt.
RAM_A5 node istype 'collapse'; " 1 pt.
RAM_A6 node istype 'collapse'; " 1 pt.
RAM_A7 node istype 'collapse'; " 1 pt.
RAM_A8 node istype 'collapse'; " 1 pt.
RAM_A9 node istype 'collapse'; " 1 pt.
RAM_D0 node istype 'collapse'; " 2 pt.
RAM_D1 node istype 'collapse'; " 2 pt.
RAM_D10 node istype 'collapse'; " 1 pt.
RAM_D11 node istype 'collapse'; " 1 pt.
RAM_D12 node istype 'collapse'; " 1 pt.
RAM_D13 node istype 'collapse'; " 1 pt.
RAM_D14 node istype 'collapse'; " 1 pt.
RAM_D15 node istype 'collapse'; " 1 pt.
RAM_D2 node istype 'collapse'; " 2 pt.
RAM_D3 node istype 'collapse'; " 2 pt.
RAM_D4 node istype 'collapse'; " 2 pt.
RAM_D5 node istype 'collapse'; " 2 pt.
RAM_D6 node istype 'collapse'; " 2 pt.
RAM_D7 node istype 'collapse'; " 2 pt.
RAM_D8 node istype 'collapse'; " 1 pt.
RAM_D9 node istype 'collapse'; " 1 pt.
SELCLK0 node istype 'collapse'; " 2 pt.
SELCLK1 node istype 'collapse'; " 2 pt.
SELCLK2 node istype 'collapse'; " 2 pt.
TRIGGER0 node istype 'collapse'; " 2 pt.
TRIGGER1 node istype 'collapse'; " 2 pt.
TRIGGER10 node istype 'collapse'; " 2 pt.
TRIGGER11 node istype 'collapse'; " 2 pt.
TRIGGER12 node istype 'collapse'; " 2 pt.
TRIGGER13 node istype 'collapse'; " 2 pt.
TRIGGER14 node istype 'collapse'; " 2 pt.
TRIGGER15 node istype 'collapse'; " 2 pt.
TRIGGER2 node istype 'collapse'; " 2 pt.
TRIGGER3 node istype 'collapse'; " 2 pt.
TRIGGER4 node istype 'collapse'; " 2 pt.
TRIGGER5 node istype 'collapse'; " 2 pt.
TRIGGER6 node istype 'collapse'; " 2 pt.
TRIGGER7 node istype 'collapse'; " 2 pt.
TRIGGER8 node istype 'collapse'; " 2 pt.
TRIGGER9 node istype 'collapse'; " 2 pt.
EQUATIONS
A0 = IO14.Q & RAM_A0.Q
# !IO14.Q & SP_A1; "--- [PT=2, FI=3, LVL=1] ---
A1 = IO14.Q & RAM_A1.Q
# !IO14.Q & SP_A2; "--- [PT=2, FI=3, LVL=1] ---
A10 = IO14.Q & RAM_A10.Q
# !IO14.Q & SP_A11; "--- [PT=2, FI=3, LVL=1] ---
A11 = IO14.Q & RAM_A11.Q
# !IO14.Q & SP_A12; "--- [PT=2, FI=3, LVL=1] ---
A12 = IO14.Q & RAM_A12.Q
# !IO14.Q & SP_A13; "--- [PT=2, FI=3, LVL=1] ---
A13 = IO14.Q & BANK0.Q
# SP_A14 & !IO14.Q; "--- [PT=2, FI=3, LVL=1] ---
A14 = IO14.Q & BANK1.Q
# SP_A15 & !IO14.Q; "--- [PT=2, FI=3, LVL=1] ---
A15 = IO14.Q & BANK2.Q
# SP_A16 & !IO14.Q; "--- [PT=2, FI=3, LVL=1] ---
A16 = IO14.Q & BANK3.Q
# SP_A17 & !IO14.Q; "--- [PT=2, FI=3, LVL=1] ---
A17 = IO14.Q & BANK4.Q
# SP_A18 & !IO14.Q; "--- [PT=2, FI=3, LVL=1] ---
A18 = SP_A19; "--- [PT=1, FI=1, LVL=1] ---
A19 = SP_A20; "--- [PT=1, FI=1, LVL=1] ---
A2 = IO14.Q & RAM_A2.Q
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