time_sim_dec.vho

可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器

---------------------------------------------------------------------------
-- XPLAOPT Version 3.33
-- VHDL Timing Model
-- Converted from JEDEC file
-- Created by Xilinx, Inc.
-- Design Name = 8b10b_decoder.blx
-- Device Name = XCR3064XL-7VQ44
-- Apr 04 10:38:23 2000
---------------------------------------------------------------------------
package pxa_pkg is
    constant tLOGI1 : time := 2500 ps;
    constant tLOGI2 : time := 3200 ps;
    constant tLOGI3 : time := 7500 ps;
    constant tFIN  : time := 2100 ps;
    constant tIN   : time := 1600 ps;
    constant tF    : time := 2100 ps;
    constant tUDA  : time := 4500 ps;
    constant tGCK  : time := 1100 ps;
    constant tLDI  : time := 500 ps;
    constant toe_slew : time := 10200 ps;
    constant tbuf_slew : time := 7700 ps;
    constant tod      : time := 5200 ps;
    constant tap2q : time := 2000 ps;
    constant tar2q : time := 2000 ps;
    constant trd   : time := 1200 ps;
    constant tbuf  : time := 2700 ps;
    constant toe   : time := 5200 ps;
end pxa_pkg;
---------------------------------------------------------------------------
-- Components Defined Here
---------------------------------------------------------------------------
-- Output Buffer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_bufif2 is
	port (O: out std_logic; I, OE, SLEW : in std_logic);
end pxa_bufif2;
architecture behavioral of pxa_bufif2 is
signal OE_local, I_local : std_logic := '0';
begin
  OE_local <= OE after toe_slew when SLEW = '1' else OE after toe;
  I_local <= I after tbuf_slew when SLEW = '1' else I after tbuf;
  O <= I_local when OE_local = '1' else 'Z' after tod;
end behavioral;

-- Multiplexer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_mux is
	port (O: out std_logic; S, A, B : in std_logic);
end pxa_mux;
architecture behavioral of pxa_mux is
begin
	O <= A when S = '1' else B;
end behavioral;

-- D Flip Flop with Asynchronous Preset/Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_dff_apar_p0 is
	port (Q : out std_logic; D, CLK, AP, AR : in std_logic);
end pxa_dff_apar_p0;
architecture behavioral of pxa_dff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
    elsif AP = '1' then
	   Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Preset/Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_tff_apar_p0 is
	port (Q : out std_logic; T, CLK, AP, AR : in std_logic);
end pxa_tff_apar_p0;
architecture behavioral of pxa_tff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
      Q_local <= '0' after tar2q;
    elsif AP = '1' then
      Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

---------------------------------------------------------------------------
-- Main VHDL Model 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity 8b10b_decoder is
    port(clk, data_in_0, data_in_1, data_in_2, data_in_3, data_in_4,
         data_in_5, data_in_6, data_in_7, data_in_8, data_in_9, frame_in,
         rst: in std_logic;
         data_out_0, data_out_1, data_out_2, data_out_3, data_out_4,
         data_out_5, data_out_6, data_out_7, err_out, frame_out, kout
         : out std_logic
         );
end 8b10b_decoder;

architecture structure of 8b10b_decoder is

-------- Signal Declaration -----------------------------------------------
signal   N212_1_COM, N212_COM, N390_1_COM, N390_COM, N798_1_COM, N798_COM,
         data_in_0_tIN, data_in_1_tIN, data_in_2_tIN, data_in_3_tIN,
         data_in_4_tIN, data_in_5_tIN, data_in_6_tIN, data_in_7_tIN,
         data_in_8_tIN, data_in_9_tIN, data_out_0_COM, data_out_0_OE,
         data_out_1_COM, data_out_1_OE, data_out_2_COM, data_out_2_OE,
         data_out_3_COM, data_out_3_OE, data_out_4_COM, data_out_4_OE,
         data_out_5_COM, data_out_5_OE, data_out_6_COM, data_out_6_OE,
         data_out_7_COM, data_out_7_OE, dec_8b10b_I_aout_AP,
         dec_8b10b_I_aout_AR, dec_8b10b_I_aout_C, dec_8b10b_I_aout_D,
         dec_8b10b_I_aout_DIN, dec_8b10b_I_aout_Q, dec_8b10b_I_aout_Q_tF,
         dec_8b10b_I_bout_AP, dec_8b10b_I_bout_AR, dec_8b10b_I_bout_C,
         dec_8b10b_I_bout_D, dec_8b10b_I_bout_DIN, dec_8b10b_I_bout_Q,
         dec_8b10b_I_bout_Q_tF, dec_8b10b_I_cout_AP, dec_8b10b_I_cout_AR,
         dec_8b10b_I_cout_C, dec_8b10b_I_cout_D, dec_8b10b_I_cout_DIN,
         dec_8b10b_I_cout_Q, dec_8b10b_I_cout_Q_tF, dec_8b10b_I_dout_AP,
         dec_8b10b_I_dout_AR, dec_8b10b_I_dout_C, dec_8b10b_I_dout_D,
         dec_8b10b_I_dout_DIN, dec_8b10b_I_dout_Q, dec_8b10b_I_dout_Q_tF,
         dec_8b10b_I_eout_AP, dec_8b10b_I_eout_AR, dec_8b10b_I_eout_C,
         dec_8b10b_I_eout_D, dec_8b10b_I_eout_DIN, dec_8b10b_I_eout_Q,
         dec_8b10b_I_eout_Q_tF, dec_8b10b_I_fout_AP, dec_8b10b_I_fout_AR,
         dec_8b10b_I_fout_C, dec_8b10b_I_fout_D, dec_8b10b_I_fout_DIN,
         dec_8b10b_I_fout_Q, dec_8b10b_I_fout_Q_tF, dec_8b10b_I_gout_AP,
         dec_8b10b_I_gout_AR, dec_8b10b_I_gout_C, dec_8b10b_I_gout_D,
         dec_8b10b_I_gout_DIN, dec_8b10b_I_gout_Q, dec_8b10b_I_gout_Q_tF,
         dec_8b10b_I_hout_AP, dec_8b10b_I_hout_AR, dec_8b10b_I_hout_C,
         dec_8b10b_I_hout_D, dec_8b10b_I_hout_DIN, dec_8b10b_I_hout_Q,
         dec_8b10b_I_hout_Q_tF, dec_8b10b_I_kout_AP, dec_8b10b_I_kout_AR,
         dec_8b10b_I_kout_C, dec_8b10b_I_kout_D, dec_8b10b_I_kout_DIN,
         dec_8b10b_I_kout_Q, dec_8b10b_I_kout_Q_tF,
         dec_8b10b_prs_state_D1_AP, dec_8b10b_prs_state_D1_AR,
         dec_8b10b_prs_state_D1_C, dec_8b10b_prs_state_D1_D,
         dec_8b10b_prs_state_D1_DIN, dec_8b10b_prs_state_D1_Q,
         dec_8b10b_prs_state_D1_Q_tF, dec_8b10b_prs_state_D2_AP,
         dec_8b10b_prs_state_D2_AR, dec_8b10b_prs_state_D2_C,
         dec_8b10b_prs_state_D2_DIN, dec_8b10b_prs_state_D2_Q,
         dec_8b10b_prs_state_D2_Q_tF, dec_8b10b_prs_state_D2_T,
         err_chk_prs_state_D1_AP, err_chk_prs_state_D1_AR,
         err_chk_prs_state_D1_C, err_chk_prs_state_D1_D,
         err_chk_prs_state_D1_DIN, err_chk_prs_state_D1_Q,
         err_chk_prs_state_D1_Q_tF, err_chk_prs_state_D2_AP,
         err_chk_prs_state_D2_AR, err_chk_prs_state_D2_C,
         err_chk_prs_state_D2_DIN, err_chk_prs_state_D2_Q,
         err_chk_prs_state_D2_Q_tF, err_chk_prs_state_D2_T, err_out_COM,
         err_out_OE, frame_in_tIN, frame_out_COM, frame_out_OE, kout_COM,
         kout_OE, prs_state_T1_AP, prs_state_T1_AR, prs_state_T1_C,
         prs_state_T1_DIN, prs_state_T1_Q, prs_state_T1_Q_tF,
         prs_state_T1_T, prs_state_T2_AP, prs_state_T2_AR, prs_state_T2_C,
         prs_state_T2_DIN, prs_state_T2_Q, prs_state_T2_Q_tF,
         prs_state_T2_T, rst_tIN: std_logic;
signal   VCC : std_logic;
signal   GND : std_logic;

component pxa_bufif2
	port (O: out std_logic; I, OE, SLEW : in std_logic);
end component;
component pxa_mux
	port (O: out std_logic; S, A, B : in std_logic);
end component;
component pxa_dff_apar_p0
	port (Q : out std_logic; D, CLK, AP, AR : in std_logic);
end component;
component pxa_tff_apar_p0
	port (Q : out std_logic; T, CLK, AP, AR : in std_logic);
end component;
begin
-- Equations:

VCC         <= '1';
GND         <= '0';
--------( N212 )-----------------------------------------------------------
N212_COM    <= not ((data_in_8_tIN and data_in_9_tIN)) after tLOGI3;
--------( N212_1 )---------------------------------------------------------
N212_1_COM  <= not ((data_in_8_tIN and data_in_9_tIN)) after tLOGI3;
--------( N390 )-----------------------------------------------------------
N390_COM    <= not ((not data_in_4_tIN and not data_in_5_tIN 
               and not data_in_7_tIN and not data_in_6_tIN)) after tLOGI3;
--------( N390_1 )---------------------------------------------------------
N390_1_COM  <= not ((not data_in_5_tIN and not data_in_6_tIN 
               and not data_in_4_tIN and not data_in_7_tIN)) after tLOGI3;
--------( N798 )-----------------------------------------------------------
N798_COM    <= not ((not data_in_8_tIN and not data_in_9_tIN))
               after tLOGI3;
--------( N798_1 )---------------------------------------------------------
N798_1_COM  <= not ((not data_in_8_tIN and not data_in_9_tIN))
               after tLOGI3;
--------( data_out_0 )-----------------------------------------------------
data_out_0_COM<= ((prs_state_T1_Q_tF and dec_8b10b_I_hout_Q_tF 
               and prs_state_T2_Q_tF)) after tLOGI1;
data_out_0_OE<= (VCC) after tFIN;
data_out_0_buf: pxa_bufif2 port map (data_out_0, data_out_0_COM, 
               data_out_0_OE, VCC);
--------( data_out_1 )-----------------------------------------------------
data_out_1_COM<= ((dec_8b10b_I_gout_Q_tF and prs_state_T1_Q_tF 
               and prs_state_T2_Q_tF)) after tLOGI1;
data_out_1_OE<= (VCC) after tFIN;
data_out_1_buf: pxa_bufif2 port map (data_out_1, data_out_1_COM, 
               data_out_1_OE, VCC);
--------( data_out_2 )-----------------------------------------------------
data_out_2_COM<= ((prs_state_T1_Q_tF and dec_8b10b_I_fout_Q_tF 
               and prs_state_T2_Q_tF)) after tLOGI1;
data_out_2_OE<= (VCC) after tFIN;
data_out_2_buf: pxa_bufif2 port map (data_out_2, data_out_2_COM, 
               data_out_2_OE, VCC);
--------( data_out_3 )-----------------------------------------------------
data_out_3_COM<= ((prs_state_T1_Q_tF and prs_state_T2_Q_tF 
               and dec_8b10b_I_eout_Q_tF)) after tLOGI1;
data_out_3_OE<= (VCC) after tFIN;
data_out_3_buf: pxa_bufif2 port map (data_out_3, data_out_3_COM, 
               data_out_3_OE, VCC);
--------( data_out_4 )-----------------------------------------------------
data_out_4_COM<= ((prs_state_T1_Q_tF and dec_8b10b_I_dout_Q_tF 
               and prs_state_T2_Q_tF)) after tLOGI1;
data_out_4_OE<= (VCC) after tFIN;
data_out_4_buf: pxa_bufif2 port map (data_out_4, data_out_4_COM, 
               data_out_4_OE, VCC);
--------( data_out_5 )-----------------------------------------------------