8b10b_decoder.npl

可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器

JDF D
// Created by Xilinx HDL_ABEL ver 5.0
PROJECT 8b10b_Decoder
DESIGN 8b10b_decoder Normal
DEVKIT XCR3064XL VQ44
MODULE main_dec.vhd
MODSTYLE decoder Normal
MODULE dec_func.vhd
MODSTYLE dec_func Normal
MODULE err_check.vhd
MODSTYLE err_check Normal
[STRATEGY-LIST]
Normal=True, 954866274
[Normal]
xplaOptMode=xcrpla3s710a, Design.TASKfitDes, 954866197, Density
xplaFoldnand=xcrpla3s710a, Design.TASKfitDes, 954866197, True
xplaResISP=xcrpla3s710a, Design.TASKfitDes, 954866197, False
xplaSLOW=xcrpla3s710a, Design.TASKfitDes, 954866197, True
xplaMaxppe=xcrpla3s710a, Design.TASKfitDes, 954866197, 37
xplaMaxbfi=xcrpla3s710a, Design.TASKfitDes, 954866197, 40
xplaMaxFanin=xcrpla3s710a, Design.TASKfitDes, 954866197, 40
xplaTimOF=xcrpla3s710a, Design.TASKfitDes, 954866197, time_sim_dec.vho
xplaTimOT=xcrpla3s710a, Design.TASKfitDes, 954866197, VHDL
_PlsOpt=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954866165, Area
_PlsOptEffort=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954866165, High
_PlsFsmEncode=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954866165, Sequential
_PlsFlattenHier=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954866165, True