8b10b.npl

可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器

JDF D
// Created by Xilinx HDL_ABEL ver 5.0
PROJECT 8b10b
DESIGN 8b10b Normal
DEVKIT XCR3064XL VQ44
MODULE dis_gen.vhd
MODSTYLE dis_gen Normal
MODULE s_gen.vhd
MODSTYLE s_gen Normal
MODULE enc_func.vhd
MODSTYLE enc_func Normal
MODULE main_enc.vhd
MODSTYLE encoder Normal
STIMULUS encoder main_tb.vhd Normal
STIMULUS encoder tst_bench.vhd Normal
PACKAGE pkg_convert.vhd Normal
PACKAGE pkg_spc_char.vhd Normal
[STRATEGY-LIST]
Normal=True, 954863251
[Normal]
xplaOptMode=xcrpla3s710a, Design.TASKfitDes, 954862883, Density
xplaFoldnand=xcrpla3s710a, Design.TASKfitDes, 954862883, True
xplaResISP=xcrpla3s710a, Design.TASKfitDes, 954862883, False
xplaSLOW=xcrpla3s710a, Design.TASKfitDes, 954862883, True
xplaMaxppe=xcrpla3s710a, Design.TASKfitDes, 954862883, 37
xplaMaxbfi=xcrpla3s710a, Design.TASKfitDes, 954862883, 40
xplaMaxFanin=xcrpla3s710a, Design.TASKfitDes, 954862883, 40
xplaTimOF=xcrpla3s710a, Design.TASKfitDes, 954862883, time_sim_enc.vho
xplaTimOT=xcrpla3s710a, Design.TASKfitDes, 954862883, VHDL
_PlsOpt=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954862847, Area
_PlsOptEffort=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954862847, High
_PlsFsmEncode=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954862847, Sequential
_PlsFlattenHier=xcrpla3s710a, Schematic.TASKrunPLSVHDL, 954862847, True
_VhdlFSimCustom=xcrpla3s710a, Module VHDL Test Bench.TASKvhdlFunSim, 954864953, enc_dec.do
_VhdlSimDo=xcrpla3s710a, Module VHDL Test Bench.TASKvhdlFunSim, 954863324, False
_VhdlRunTime=xcrpla3s710a, Module VHDL Test Bench.TASKvhdlFunSim, 954863324, 0
_VhdlSignalWin=xcrpla3s710a, Module VHDL Test Bench.TASKvhdlFunSim, 954863324, False
_VhdlWaveWin=xcrpla3s710a, Module VHDL Test Bench.TASKvhdlFunSim, 954863324, False
_VhdlStructWin=xcrpla3s710a, Module VHDL Test Bench.TASKvhdlFunSim, 954863324, False