h16550tsw.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550 UART
//
//  File          : h16550tsw.v
//
//  Dependencies  : h16550.v
//
//  Model Type    : Synthesizable Core
//
//  Description   : Bidirectional Data Bus Wrapper for h16550 UART with FIFO
//
//  Designer      : JS
//
//  QA Engineer   : JH
//
//  Creation Date : 15-January-2002
//
//  Last Update   : 20-June-2003
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/18/02    VHDL Release
//                  1.2 - 04/16/02    Performance (size) improved
//                  2.0 - 06/20/03    Rename RXRDY and TXRDY to RXRDYN and TXRDYN
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module h16550tsw (mr, clk, rclk, cs0, cs1, cs2n, rd, wr, ctsn, dcdn, dsrn, rin, sin, adsn, a, d, ddis, sout, baudoutn, dtrn, rtsn, out1n, out2n, intr, rxrdyn, txrdyn);

   `include "h16550_params.v"

   input mr; // Master Reset
   input clk; // System Clock
   input rclk; // Receiver Clock
   input cs0; // Chip Select 0
   input cs1; // Chip Select 1
   input cs2n; // Chip Select 2
   input rd; // Read enable
   input wr; // Write enable
   input ctsn; // Clear To Send
   input dcdn; // Data Carrier Detect
   input dsrn; // Data Set Ready
   input rin; // Ring indicator
   input sin; // Serial Input
   input adsn; // Address strobe enable
   input[2:0] a; // Address
   inout[7:0] d; // I/O bus
   wire[7:0] d;
   wire[7:0] d_xhdl0;
   output ddis; // Driver Disable
   wire ddis;
   output sout; // Serial output
   wire sout;
   output baudoutn; // Baud Out
   wire baudoutn;
   output dtrn; // Data Terminal ready
   wire dtrn;
   output rtsn; // Request to send enable
   wire rtsn;
   output out1n; // Output 1
   wire out1n;
   output out2n; // Output 2
   wire out2n;
   output intr; // interrupt
   wire intr;
   output rxrdyn; // Receiver ready
   wire rxrdyn;
   output txrdyn; 
   wire txrdyn;

   reg cs_latched; 
   wire cs; 
   reg[2:0] a_latched; 
   wire ddis_int; 
   wire[7:0] din; 
   wire[7:0] dout; 

   assign d = d_xhdl0;

   assign ddis = ddis_int ; 
   assign cs = (cs0 == 1'b1 & cs1 == 1'b1 & cs2n == 1'b0) ? 1'b1 : 1'b0 ; 
   assign d = (ddis_int == 1'b0) ? dout : 8'bZZZZZZZZ ; 
   assign din = d ; 

   always @(mr or adsn or cs or a)
   begin
      if (mr == 1'b1)
      begin
         cs_latched <= 1'b0 ; 
         a_latched <= 3'b000 ; 
      end
      else if (adsn == 1'b0)
      begin
         cs_latched <= cs ; 
         a_latched <= a ; 
      end 
   end 
   h16550 u_h16550 (.mr(mr), .clk(clk), .rclk(rclk), .cs(cs_latched), .rd(rd), .wr(wr), .ctsn(ctsn), .dcdn(dcdn), .dsrn(dsrn), .rin(rin), .sin(sin), .a(a_latched), .din(din), .ddis(ddis_int), .sout(sout), .baudoutn(baudoutn), .dtrn(dtrn), .rtsn(rtsn), .out1n(out1n), .out2n(out2n), .intr(intr), .rxrdyn(rxrdyn), .txrdyn(txrdyn), .dout(dout)); 
endmodule