uart_fifo.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550S UART
//
//  File          : uart_fifo.v
//
//  Dependencies  : none
//
//  Model Type    : Synthesizable Core
//
//  Description   : h16550 FIFO (register or RAM type)
//
//  Designer      : JV
//
//  QA Engineer   : JH
//
//  Creation Date : 02-January-2002
//
//  Last Update   : 20-June-2003
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/22/02    VHDL Release
//                  1.2 - 04/23/02    Reduce Receiver's RAMs
//                                    Reduce Receiver and Transmitter read/write
//                                    address to 4 bits
//                  2.0 - 06/20/03    Combined both fifo_ram, and fifo_reg to uart_fifo
//                                    Renamed fifo to uart_fifo
//                                    Add FIFOREG generic to choose fifo_ram or fifo_reg typ
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module uart_fifo (rclk, wr, reset_rxfifo, reset_txfifo, write_thr, rxfifo_wr,
d, rxf, rxwr_addr, rxrd_addr, txwr_addr, txrd_addr, threg, rbreg, rbreg_rxf);

   `include "h16550_params.v"

   // it is used for synthesis only, if the fifo is register type
   //`define FIFOREG;

   input rclk; // System Clock
   input wr; // Write Enable
   input reset_rxfifo; // Reset receiver fifo
   input reset_txfifo; // Reset transceiver fifo
   input write_thr; // Write Transmit holding register enable
   input rxfifo_wr; // Write Receiver Fifo enable
   input[DATA_WIDTH - 1:0] d; // Data input
   input[10:0] rxf; // Receiver Fifo data
   input[3:0] rxwr_addr; // Receiver Write Fifo address
   input[3:0] rxrd_addr; // Receiver Read fifo address
   input[3:0] txwr_addr; // Transmitter Write Fifo address
   input[3:0] txrd_addr; // Transmitter Read Fifo address
   output[DATA_WIDTH - 1:0] threg; // Transmitter hold register
   reg[DATA_WIDTH - 1:0] threg;
   output[DATA_WIDTH - 1:0] rbreg; // Receiver buffer register
   wire[DATA_WIDTH - 1:0] rbreg;
   output[2:0] rbreg_rxf; 
   wire[2:0] rbreg_rxf;

   reg[7:0] txf[0:15]; 
   reg[10:0] rxfdata[0:15]; 
   reg[10:0] rbreg_rxf_int; 

//----------------------
// FIFO REGISTER TYPE
//----------------------
`ifdef FIFOREG
   //-----------
   // RCVR FIFO 
   //-----------
   always @(posedge reset_rxfifo or posedge rclk)
   begin : rx_fifo_write
      if (reset_rxfifo == 1'b1)
      begin
         rxfdata[0] <= 11'b00000000000 ; 
         rxfdata[1] <= 11'b00000000000 ; 
         rxfdata[2] <= 11'b00000000000 ; 
         rxfdata[3] <= 11'b00000000000 ; 
         rxfdata[4] <= 11'b00000000000 ; 
         rxfdata[5] <= 11'b00000000000 ; 
         rxfdata[6] <= 11'b00000000000 ; 
         rxfdata[7] <= 11'b00000000000 ; 
         rxfdata[8] <= 11'b00000000000 ; 
         rxfdata[9] <= 11'b00000000000 ; 
         rxfdata[10] <= 11'b00000000000 ; 
         rxfdata[11] <= 11'b00000000000 ; 
         rxfdata[12] <= 11'b00000000000 ; 
         rxfdata[13] <= 11'b00000000000 ; 
         rxfdata[14] <= 11'b00000000000 ; 
         rxfdata[15] <= 11'b00000000000 ; 
      end
      else
      begin
         if (rxfifo_wr == 1'b1)
         begin
            case (rxwr_addr)
               // receive from serial in
               4'b0001 : rxfdata[1] <= rxf ; 
               4'b0010 : rxfdata[2] <= rxf ; 
               4'b0011 : rxfdata[3] <= rxf ; 
               4'b0100 : rxfdata[4] <= rxf ; 
               4'b0101 : rxfdata[5] <= rxf ; 
               4'b0110 : rxfdata[6] <= rxf ; 
               4'b0111 : rxfdata[7] <= rxf ;
               4'b1000 : rxfdata[8] <= rxf ; 
               4'b1001 : rxfdata[9] <= rxf ; 
               4'b1010 : rxfdata[10] <= rxf ; 
               4'b1011 : rxfdata[11] <= rxf ; 
               4'b1100 : rxfdata[12] <= rxf ; 
               4'b1101 : rxfdata[13] <= rxf ; 
               4'b1110 : rxfdata[14] <= rxf ; 
               4'b1111 : rxfdata[15] <= rxf ; 
               default : rxfdata[0] <= rxf ; 
            endcase 
         end 
      end 
   end 

   always @(rxrd_addr or rxfdata[0] or rxfdata[1] or rxfdata[2] or rxfdata[3] or rxfdata[4] or
            rxfdata[5] or rxfdata[6] or rxfdata[7] or rxfdata[8] or rxfdata[9] or rxfdata[10] or
            rxfdata[11] or rxfdata[12] or rxfdata[13] or rxfdata[14] or rxfdata[15])
   begin : rx_fifo_read
      case (rxrd_addr)
         4'b0001 : rbreg_rxf_int <= rxfdata[1] ; 
         4'b0010 : rbreg_rxf_int <= rxfdata[2] ; 
         4'b0011 : rbreg_rxf_int <= rxfdata[3] ; 
         4'b0100 : rbreg_rxf_int <= rxfdata[4] ; 
         4'b0101 : rbreg_rxf_int <= rxfdata[5] ; 
         4'b0110 : rbreg_rxf_int <= rxfdata[6] ; 
         4'b0111 : rbreg_rxf_int <= rxfdata[7] ; 
         4'b1000 : rbreg_rxf_int <= rxfdata[8] ; 
         4'b1001 : rbreg_rxf_int <= rxfdata[9] ; 
         4'b1010 : rbreg_rxf_int <= rxfdata[10] ; 
         4'b1011 : rbreg_rxf_int <= rxfdata[11] ; 
         4'b1100 : rbreg_rxf_int <= rxfdata[12] ; 
         4'b1101 : rbreg_rxf_int <= rxfdata[13] ; 
         4'b1110 : rbreg_rxf_int <= rxfdata[14] ; 
         4'b1111 : rbreg_rxf_int <= rxfdata[15] ; 
         default : rbreg_rxf_int <= rxfdata[0] ; 
      endcase 
   end 

   assign rbreg = rbreg_rxf_int[10:3] ; 
   assign rbreg_rxf = rbreg_rxf_int[2:0] ; 

   //-----------
   // XMIT FIFO 
   //-----------
   always @(posedge reset_txfifo or negedge wr)
   begin : tx_fifo_write
      if (reset_txfifo == 1'b1)
      begin
         txf[0] <= 8'b00000000 ; 
         txf[1] <= 8'b00000000 ; 
         txf[2] <= 8'b00000000 ; 
         txf[3] <= 8'b00000000 ; 
         txf[4] <= 8'b00000000 ; 
         txf[5] <= 8'b00000000 ; 
         txf[6] <= 8'b00000000 ; 
         txf[7] <= 8'b00000000 ; 
         txf[8] <= 8'b00000000 ; 
         txf[9] <= 8'b00000000 ; 
         txf[10] <= 8'b00000000 ; 
         txf[11] <= 8'b00000000 ; 
         txf[12] <= 8'b00000000 ; 
         txf[13] <= 8'b00000000 ; 
         txf[14] <= 8'b00000000 ; 
         txf[15] <= 8'b00000000 ; 
      end
      else
      begin
         if (write_thr == 1'b1)
         begin
            case (txwr_addr)
               4'b0001 : txf[1] <= d ; 
               4'b0010 : txf[2] <= d ; 
               4'b0011 : txf[3] <= d ; 
               4'b0100 : txf[4] <= d ; 
               4'b0101 : txf[5] <= d ; 
               4'b0110 : txf[6] <= d ; 
               4'b0111 : txf[7] <= d ; 
               4'b1000 : txf[8] <= d ; 
               4'b1001 : txf[9] <= d ; 
               4'b1010 : txf[10] <= d ; 
               4'b1011 : txf[11] <= d ; 
               4'b1100 : txf[12] <= d ; 
               4'b1101 : txf[13] <= d ; 
               4'b1110 : txf[14] <= d ; 
               4'b1111 : txf[15] <= d ; 
               default : txf[0] <= d ; 
            endcase 
         end 
      end 
   end 

   always @(txrd_addr or txf[0] or txf[1] or txf[2] or txf[3] or txf[4] or txf[5] or txf[6] or
            txf[7] or txf[8] or txf[9] or txf[10] or txf[11] or txf[12] or txf[13] or txf[14] or
            txf[15])
   begin
      case (txrd_addr)
         4'b0000 : threg <= txf[0] ; 
         4'b0001 : threg <= txf[1] ; 
         4'b0010 : threg <= txf[2] ; 
         4'b0011 : threg <= txf[3] ; 
         4'b0100 : threg <= txf[4] ; 
         4'b0101 : threg <= txf[5] ; 
         4'b0110 : threg <= txf[6] ; 
         4'b0111 : threg <= txf[7] ; 
         4'b1000 : threg <= txf[8] ; 
         4'b1001 : threg <= txf[9] ; 
         4'b1010 : threg <= txf[10] ; 
         4'b1011 : threg <= txf[11] ; 
         4'b1100 : threg <= txf[12] ; 
         4'b1101 : threg <= txf[13] ; 
         4'b1110 : threg <= txf[14] ; 
         default : threg <= txf[15] ; 
      endcase 
   end 

//----------------------
// FIFO RAM TYPE
//----------------------
`else
   //-----------
   // RCVR FIFO 
   //-----------
   always @(posedge rclk)
   begin : rx_fifo_write
      if (rxfifo_wr == 1'b1)
      begin
         rxfdata[(rxwr_addr)] <= rxf ; 
      end  
   end 

   always @(rxrd_addr or rxfdata[0] or rxfdata[1] or rxfdata[2] or rxfdata[3] or rxfdata[4] or rxfdata[5] or rxfdata[6] or rxfdata[7] or rxfdata[8] or rxfdata[9] or rxfdata[10] or rxfdata[11] or rxfdata[12] or rxfdata[13] or rxfdata[14] or rxfdata[15])
   begin : rx_fifo_read
      rbreg_rxf_int <= rxfdata[(rxrd_addr)] ; 
   end 

   assign rbreg = rbreg_rxf_int[10:3] ; 
   assign rbreg_rxf = rbreg_rxf_int[2:0] ; 

   //-----------
   // XMIT FIFO 
   //-----------
   always @(posedge wr)
   begin : tx_fifo_write
      if (write_thr == 1'b1)
      begin
         txf[(txwr_addr)] <= d ; 
      end  
   end 

   always @(txrd_addr or txf[0] or txf[1] or txf[2] or txf[3] or txf[4] or txf[5] or txf[6] or txf[7] or txf[8] or txf[9] or txf[10] or txf[11] or txf[12] or txf[13] or txf[14] or txf[15])
   begin
      threg <= txf[(txrd_addr)] ; 
   end 

`endif

endmodule