uart_fifo_altera.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550 UART
//
//  File          : fifo_stratix.v
//
//  Dependencies  : none 
//
//  Model Type    : Synthesizable Core
//
//  Description   : h16550 FIFO implemented using Altera embedded memory
//
//  Designer      : JV
//
//  QA Engineer   : JH
//
//  Creation Date : 02-January-2002
//
//  Last Update   : 20-June-2003
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/18/02    VHDL Release
//                  1.2 - 04/16/02    Reduce Receiver's RAMs
//                                    Reduce Receiver and Transmitter read/write 
//                                    address to 4 bits
//                  2.0 - 06/20/03    Renamed fifo to uart_fifo  
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module uart_fifo (rclk, wr, reset_rxfifo, reset_txfifo, write_thr, rxfifo_wr, d, rxf, rxwr_addr, rxrd_addr, txwr_addr, txrd_addr, threg, rbreg, rbreg_rxf);

   `include "h16550_params.v"

   parameter[0:0] FIFOREG  = 0;

   input rclk; // Receiver Clock
   input wr; // Write Enable
   input reset_rxfifo; // Reset receiver fifo
   input reset_txfifo; // Reset transceiver fifo
   input write_thr; // Write Transmit holding register enable
   input rxfifo_wr; // Write Receiver Fifo enable
   input[DATA_WIDTH - 1:0] d; // Data input
   input[10:0] rxf; // Receiver Fifo data
   input[3:0] rxwr_addr; // Receiver Write Fifo address
   input[3:0] rxrd_addr; // Receiver Read fifo address
   input[3:0] txwr_addr; // Transmitter Write Fifo address
   input[3:0] txrd_addr; // Transmitter Read Fifo address
   output[DATA_WIDTH - 1:0] threg; // Transmitter hold register
   wire[DATA_WIDTH - 1:0] threg;
   output[DATA_WIDTH - 1:0] rbreg; // Receiver buffer register
   wire[DATA_WIDTH - 1:0] rbreg;
   output[2:0] rbreg_rxf; 
   wire[2:0] rbreg_rxf;

   reg[10:0] rxfdata[0:15]; 
   reg[10:0] rbreg_rxf_int; 

   //-----------
   // RCVR FIFO 
   //-----------
   always @(posedge rclk)
   begin : RX_FIFO_write
      if (rxfifo_wr == 1'b1)
      begin
         rxfdata[(rxwr_addr)] <= rxf ; 
      end 
   end 

   always @(rxrd_addr or rxfdata[0] or rxfdata[1] or rxfdata[2] or rxfdata[3] or rxfdata[4] or rxfdata[5] or rxfdata[6] or rxfdata[7] or rxfdata[8] or rxfdata[9] or rxfdata[10] or rxfdata[11] or rxfdata[12] or rxfdata[13] or rxfdata[14] or
rxfdata[15])
   begin : RX_FIFO_read
      rbreg_rxf_int <= rxfdata[(rxrd_addr)] ; 
   end 

   assign rbreg = rbreg_rxf_int[10:3] ; 
   assign rbreg_rxf = rbreg_rxf_int[2:0] ; 

   //------------
   // XMIT FIFO 
   //------------

   lpm_ram_dp utx_lpmfifo(.rdclock(), .rdclken(), .rdaddress(txrd_addr), .rden(), .data(d), .wraddress(txwr_addr), .wren(write_thr), .wrclock(wr), .wrclken(), .q(threg)); 

   defparam 
      utx_lpmfifo.lpm_width = 8;
      utx_lpmfifo.lpm_widthad = 4;
      utx_lpmfifo.lpm_numwords = 16;
      utx_lpmfifo.lpm_indata = "registered";
      utx_lpmfifo.lpm_outdata = "unregistered";
      utx_lpmfifo.lpm_rdaddress_control = "unregistered";
      utx_lpmfifo.lpm_wraddress_control = "registered";
      utx_lpmfifo.lpm_file = "unused";
      utx_lpmfifo.lpm_type = "lpm_ram_dp";
      utx_lpmfifo.lpm_hint = "unused";


endmodule