rwcontrol.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550 UART
//
//  File          : rwcontrol.v
//
//  Dependencies  : none
//
//  Model Type    : Synthesizable Core
//
//  Description   : h16550 rwcontrol
//
//  Designer      : JU
//
//  QA Engineer   : JH
//
//  Creation Date : 02-January-2002
//
//  Last Update   : 20-June-2003
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/18/02    VHDL Release
//                  1.2 - 04/16/02    Performance (size) improved
//                  2.0 - 06/20/03    Renamed interface to rwcontrol
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module rwcontrol (cs, rd, mr, clk, fcreg0, a, rbreg, dmreg, dlreg, iereg, iireg, lcreg, lsreg, mcreg, msreg, sreg, ena_ier, ena_lcr, ena_mcr, ena_sr, read_msr, read_iir, read_lsr, write_thr, write_dlr, write_dmr, ddis, d);

   `include "h16550_params.v"

   input cs; // Latched Chip Select
   input rd; // Read Enable
   input mr; // Master Reset
   input clk; // System Clock
   input fcreg0; // Fifo Control Register bit0
   input[ADDR_WIDTH - 1:0] a; // Latched address
   input[DATA_WIDTH - 1:0] rbreg; // Receiver buffer register
   input[DATA_WIDTH - 1:0] dmreg; // MSB divisor register
   input[DATA_WIDTH - 1:0] dlreg; // LSB divisor register
   input[3:0] iereg; // Interrupt enable register
   input[3:0] iireg; // Interrupt Status register
   input[DATA_WIDTH - 1:0] lcreg; // Line control register
   input[DATA_WIDTH - 1:0] lsreg; // Line status register
   input[4:0] mcreg; // Modem control register
   input[DATA_WIDTH - 1:0] msreg; // Modem status register
   input[DATA_WIDTH - 1:0] sreg; // Scratch pad register
   output ena_ier; // Interrupt Enable register enable
   reg ena_ier;
   output ena_lcr; // Line control register enable
   reg ena_lcr;
   output ena_mcr; // Modem control register enable
   reg ena_mcr;
   output ena_sr; // Scratch pad register enable
   reg ena_sr;
   output read_msr; // Read Modem status register enable
   reg read_msr;
   output read_iir; // Read interrupt status register enable
   reg read_iir;
   output read_lsr; // Read line status register enable
   reg read_lsr;
   output write_thr; // Write Transmitter holding register enable
   reg write_thr;
   output write_dlr; // Write LSB divisor register enable
   reg write_dlr;
   output write_dmr; // Write MSB divisor register enable
   reg write_dmr;
   output ddis; // Data bus driver disable
   reg ddis;
   output[DATA_WIDTH - 1:0] d; 
   reg[DATA_WIDTH - 1:0] d;

   wire lcreg7; 
   wire[3:0] lcreg_a; 
   reg[DATA_WIDTH - 1:0] d_out_000; 
   reg[DATA_WIDTH - 1:0] d_out_001; 
   reg[DATA_WIDTH - 1:0] msreg_latched; 
   reg[3:0] iireg_latched; 

   assign lcreg7 = lcreg[7] ; 

   //---------------------------------------
   // Select the register when CPU reads it
   //---------------------------------------
   always @(a or d_out_000 or d_out_001 or iireg_latched or lcreg or mcreg or 
            msreg_latched or sreg or lsreg or fcreg0)
   begin
      case (a)
         3'b000 :
                  begin
                     d <= d_out_000 ; // Receiver Buffer/Divisor Latch (LSB) register
                  end
         3'b001 :
                  begin
                     d <= d_out_001 ; // Interrupt enable/Divisor Latch (MSB) register
                  end
         3'b010 :
                  begin
                     d <= ({fcreg0, fcreg0, 2'b00, iireg_latched}) ; // Interrupt status register
                  end
         3'b011 :
                  begin
                     d <= lcreg ; // Line control register
                  end
         3'b100 :
                  begin
                     d <= ({3'b000, mcreg}) ; // MODEM control register
                  end
         3'b101 :
                  begin
                     d <= lsreg ; // Line status register
                  end
         3'b110 :
                  begin
                     d <= msreg_latched ; // Modem status register
                  end
         default :
                  begin
                     d <= sreg ; // Scratch register
                  end
      endcase 
   end 
   assign lcreg_a = ({lcreg7, a}) ; 

   //------------------------------------------------
   // Synchronize MS Register
   // Update the modem status reg based on BRG clock
   // so that the READ is always stable
   //------------------------------------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         msreg_latched <= {1{1'b0}} ; 
         iireg_latched <= 4'b0001 ; 
      end
      else
      begin
         if (rd == 1'b0)
         begin
            msreg_latched <= msreg ; 
            iireg_latched <= iireg ; 
         end 
      end 
   end 

   //-------------------------------------------------
   // Select RBREG IEREG DLREG or DMREG to output MUX
   //-------------------------------------------------
   always @(lcreg7 or rbreg or dlreg)
   begin
      if (lcreg7 == 1'b0)
      begin
         d_out_000 <= rbreg ; // Receive buffer register from RCVR FIFO
      end
      else
      begin
         d_out_000 <= dlreg ; // Divisor (latch) LSB register
      end 
   end 

   always @(lcreg7 or iereg or dmreg)
   begin
      if (lcreg7 == 1'b0)
      begin
         d_out_001 <= ({4'b0000, iereg}) ; // Interrupt enable register
      end
      else
      begin
         d_out_001 <= dmreg ; // Divisor (latch) MSB register
      end 
   end 

   //---------------------------------------------------
   // Generate enable signals when writing to registers
   //---------------------------------------------------
   always @(cs or lcreg_a)
   begin
      write_thr <= 1'b0 ; 
      write_dlr <= 1'b0 ; 
      write_dmr <= 1'b0 ; 
      ena_ier <= 1'b0 ; 
      ena_lcr <= 1'b0 ; 
      ena_mcr <= 1'b0 ; 
      ena_sr <= 1'b0 ; 
      read_msr <= 1'b0 ; 
      read_lsr <= 1'b0 ; 
      read_iir <= 1'b0 ; 
      if (cs == 1'b1)
      begin
         case (lcreg_a)
            4'b0000 :
                     begin
                        write_thr <= 1'b1 ; // Transmitter holding register
                     end
            4'b0001 :
                     begin
                        ena_ier <= 1'b1 ; // Interrupt enable register
                     end
            4'b1000 :
                     begin
                        write_dlr <= 1'b1 ; // divisor (latch) LSB register
                     end
            4'b1001 :
                     begin
                        write_dmr <= 1'b1 ; // divisor (latch) MSB register
                     end
            4'b0010, 4'b1010 :
                     begin
                        read_iir <= 1'b1 ; // Interrupt identification register (read)
                     end
            4'b0011, 4'b1011 :
                     begin
                        ena_lcr <= 1'b1 ; // Line control register
                     end
            4'b0100, 4'b1100 :
                     begin
                        ena_mcr <= 1'b1 ; // MODEM control register
                     end
            4'b0101, 4'b1101 :
                     begin
                        read_lsr <= 1'b1 ; // Line Status register
                     end
            4'b0110, 4'b1110 :
                     begin
                        read_msr <= 1'b1 ; // MODEM STATUS register
                     end
            default :
                     begin
                        ena_sr <= 1'b1 ; // "0111"|"1111" Scratch register
                     end
         endcase 
      end 
   end 

   always @(cs or rd)
   begin
      ddis <= 1'b1 ; 
      if (cs == 1'b1 & rd == 1'b1)
      begin
         ddis <= 1'b0 ; 
      end 
   end 
endmodule