txblock.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

   always @(txbaud or state or parity or lcreg or tsreg or txfifo_empty or 
            sout_int)
   begin : state_combo_process
      next_state <= state ; 
      invert_parity <= 1'b0 ; 
      parity_lcreg4 <= 1'b0 ; 
      sout_bit <= sout_int ; 
      temt1 <= 1'b0 ; 
      case (state)
         WAITING1 :
                  begin
                     sout_bit <= 1'b1 ; 
                     parity_lcreg4 <= 1'b1 ; 
                     if (txfifo_empty == 1'b0)
                     begin
                        // SEND_START
                        next_state <= SEND_START1 ; 
                        temt1 <= 1'b0 ; 
                        sout_bit <= START ; 
                     end
                     else
                     begin
                        next_state <= WAITING1 ; 
                        temt1 <= 1'b1 ; 
                        sout_bit <= 1'b1 ; 
                     end 
                  end
         SEND_START1 :
                  begin
                     next_state <= SEND_START2 ; 
                  end
         SEND_START2 :
                  begin
                     next_state <= SEND1_BIT0 ; 
                     sout_bit <= tsreg[0] ; // LSB
                     if ((tsreg[0]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT0 :
                  begin
                     next_state <= SEND2_BIT0 ; 
                  end
         SEND2_BIT0 :
                  begin
                     next_state <= SEND1_BIT1 ; 
                     sout_bit <= tsreg[1] ; //1
                     if ((tsreg[1]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT1 :
                  begin
                     next_state <= SEND2_BIT1 ; 
                  end
         SEND2_BIT1 :
                  begin
                     next_state <= SEND1_BIT2 ; 
                     sout_bit <= tsreg[2] ; //2
                     if ((tsreg[2]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT2 :
                  begin
                     next_state <= SEND2_BIT2 ; 
                  end
         SEND2_BIT2 :
                  begin
                     next_state <= SEND1_BIT3 ; 
                     sout_bit <= tsreg[3] ; //3
                     if ((tsreg[3]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT3 :
                  begin
                     next_state <= SEND2_BIT3 ; 
                  end
         SEND2_BIT3 :
                  begin
                     next_state <= SEND1_BIT4 ; 
                     sout_bit <= tsreg[4] ; //4
                     if ((tsreg[4]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT4 :
                  begin
                     next_state <= SEND2_BIT4 ; 
                  end
         SEND2_BIT4 :
                  begin
                     if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b1)
                     begin
                        next_state <= SEND1_PARITY ; // 5 bits, parity
                        if ((lcreg[5]) == 1'b1)
                        begin
                           sout_bit <= ~lcreg[4] ; 
                        end
                        else
                        begin
                           sout_bit <= parity ; 
                        end 
                     end
                     else if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b0)
                     begin
                        next_state <= SEND1_STOP0 ; // 5 bits, no parity
                        sout_bit <= STOP ; 
                     end
                     else
                     begin
                        next_state <= SEND1_BIT5 ; // 6 bits or more
                        sout_bit <= tsreg[5] ; // 5
                     end 
                     if ((tsreg[5]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT5 :
                  begin
                     next_state <= SEND2_BIT5 ; 
                  end
         SEND2_BIT5 :
                  begin
                     if ((lcreg[0]) == 1'b1 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b1)
                     begin
                        next_state <= SEND1_PARITY ; // 6 bits, parity
                        if ((lcreg[5]) == 1'b1)
                        begin
                           sout_bit <= ~lcreg[4] ; 
                        end
                        else
                        begin
                           sout_bit <= parity ; 
                        end 
                     end
                     else if ((lcreg[0]) == 1'b1 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b0)
                     begin
                        next_state <= SEND1_STOP0 ; // 6 bits, no parity
                        sout_bit <= STOP ; 
                     end
                     else
                     begin
                        next_state <= SEND1_BIT6 ; // 7 bits or more
                        sout_bit <= tsreg[6] ; //6
                     end 
                     if ((tsreg[6]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT6 :
                  begin
                     next_state <= SEND2_BIT6 ; 
                  end
         SEND2_BIT6 :
                  begin
                     if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b1 & (lcreg[3]) == 1'b1)
                     begin
                        next_state <= SEND1_PARITY ; // 7 bits, parity
                        if ((lcreg[5]) == 1'b1)
                        begin
                           sout_bit <= ~lcreg[4] ; 
                        end
                        else
                        begin
                           sout_bit <= parity ; 
                        end 
                     end
                     else if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b1 & (lcreg[3]) == 1'b0)
                     begin
                        next_state <= SEND1_STOP0 ; // 7 bits, no parity
                        sout_bit <= STOP ; // 7
                     end
                     else
                     begin
                        next_state <= SEND1_BIT7 ; // 8 bits
                        sout_bit <= tsreg[7] ; //7
                     end 
                     if ((tsreg[7]) == 1'b1)
                     begin
                        invert_parity <= 1'b1 ; 
                     end 
                  end
         SEND1_BIT7 :
                  begin
                     next_state <= SEND2_BIT7 ; 
                  end
         SEND2_BIT7 :
                  begin
                     if ((lcreg[3]) == 1'b1)
                     begin
                        next_state <= SEND1_PARITY ; // parity
                        if ((lcreg[5]) == 1'b1)
                        begin
                           sout_bit <= ~lcreg[4] ; 
                        end
                        else
                        begin
                           sout_bit <= parity ; 
                        end 
                     end
                     else
                     begin
                        next_state <= SEND1_STOP0 ; // no parity
                        sout_bit <= STOP ; // STOP1
                     end 
                  end
         SEND1_PARITY :
                  begin
                     next_state <= SEND2_PARITY ; 
                  end
         SEND2_PARITY :
                  begin
                     next_state <= SEND1_STOP0 ; // stop
                     sout_bit <= STOP ; //  STOP1 bit
                  end
         SEND1_STOP0 :
                  begin
                     next_state <= SEND2_STOP0 ; 
                  end
         SEND2_STOP0 :
                  begin
                     if ((lcreg[2]) == 1'b0 & txfifo_empty == 1'b1)
                     begin
                        next_state <= WAITING1 ; // 1 STOP bit
                        sout_bit <= 1'b1 ; //  STOP1 bit
                        temt1 <= 1'b1 ; 
                     end
                     else if ((lcreg[2]) == 1'b0)
                     begin
                        next_state <= SEND_START1 ; 
                        sout_bit <= START ; // START
                        parity_lcreg4 <= 1'b1 ; 
                        temt1 <= 1'b0 ; 
                     end
                     else if ((lcreg[1]) == 1'b0 & (lcreg[0]) == 1'b0)
                     begin
                        next_state <= SEND2_STOP1 ; // 1.5 STOP bits
                        sout_bit <= STOP ; // STOP1
                     end
                     else
                     begin
                        next_state <= SEND1_STOP1 ; // 2 STOP bits
                        sout_bit <= STOP ; // STOP1
                     end 
                  end
         SEND1_STOP1 :
                  begin
                     next_state <= SEND2_STOP1 ; 
                  end
         SEND2_STOP1 :
                  begin
                     if (txfifo_empty == 1'b0)
                     begin
                        // SEND_BIT0
                        next_state <= SEND_START1 ; 
                        temt1 <= 1'b0 ; 
                        sout_bit <= START ; // START
                        parity_lcreg4 <= 1'b1 ; 
                     end
                     else
                     begin
                        next_state <= WAITING1 ; // 1 STOP bit
                        temt1 <= 1'b1 ; 
                        sout_bit <= 1'b1 ; //  ONE
                     end 
                  end
      endcase 
   end 
endmodule