fifoctrl.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

   // In the fifo mode this FE is associated with the particular
   // character in the fifo it applies to. This error is revealed to the
   // CPU when its associated character is at the top of the fifo
   //---------------------------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         lsreg_b3 <= 1'b0 ; 
      end
      else
      begin
         if (((lsreg[3]) == 1'b0 & (rxf[1]) == 1'b1 & (fcreg0 == 1'b0 | (rxfifo_empty_int == 1'b1 & fcreg0 == 1'b1))) | ((fcreg[1]) == 1'b1 & (lsreg[3]) == 1'b1))
         begin
            lsreg_b3 <= 1'b1 ; // set FE
         end 
         if ((fcreg0 == 1'b1 & prevrd_rbr_dly == 1'b1 & rd == 1'b0) & (rxfifo_empty_int == 1'b0) & ((lsreg[3]) == 1'b0 & (rbreg_rxf[1]) == 1'b1))
         begin
            lsreg_b3 <= 1'b1 ; // set FE
         end 
         if (prevrd_lsr == 1'b1 & rd == 1'b0 & (lsreg[3]) == 1'b1)
         begin
            lsreg_b3 <= 1'b0 ; // reset FE
         end 
      end 
   end 

   //---------------------------------------
   // the received data character have BI
   // In the fifo mode this BI is associated with the particular
   // character in the fifo it applies to. This error is revealed to the
   // CPU when its associated character is at the top of the fifo
   //---------------------------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         lsreg_b4 <= 1'b0 ; 
      end
      else
      begin
         if (((lsreg[4]) == 1'b0 & (rxf[2]) == 1'b1 & (fcreg0 == 1'b0 | (rxfifo_empty_int == 1'b1 & fcreg0 == 1'b1))) | ((fcreg[1]) == 1'b1 & (lsreg[4]) == 1'b1))
         begin
            lsreg_b4 <= 1'b1 ; // set BI
         end 
         if ((fcreg0 == 1'b1 & prevrd_rbr_dly == 1'b1 & rd == 1'b0) & (rxfifo_empty_int == 1'b0) & ((lsreg[4]) == 1'b0 & (rbreg_rxf[2]) == 1'b1))
         begin
            lsreg_b4 <= 1'b1 ; // set BI
         end 
         if (prevrd_lsr == 1'b1 & rd == 1'b0 & (lsreg[4]) == 1'b1)
         begin
            lsreg_b4 <= 1'b0 ; // reset BI
         end 
      end 
   end 

   //------------------------------
   // LSREG7 signal transmit logic
   //-------------------------------
   always @(posedge mr or posedge rclk)
   begin
      if (mr == 1'b1)
      begin
         fifo_err_add <= 4'b0000 ; 
      end
      else
      begin
         if (write_rxfifo == 1'b1 & ((rxf[2]) == 1'b1 | (rxf[1]) == 1'b1 | (rxf[0]) == 1'b1) & rxfifo_full_int == 1'b0)
         begin
            fifo_err_add <= rxwr_addr ; 
         end 
      end 
   end 

   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         lsreg_b7 <= 1'b0 ; 
      end
      else
      begin
         if ((write_rxfifo == 1'b1 & ((rxf[2]) == 1'b1 | (rxf[1]) == 1'b1 | (rxf[0]) == 1'b1) & rxfifo_full_int == 1'b0) & ((lsreg[7]) == 1'b0 & fcreg0 == 1'b1))
         begin
            lsreg_b7 <= 1'b1 ; // sets LSREG(7) bit if not pending
         end 
         if (prevrd_rbr == 1'b1 & rd == 1'b0 & fifo_err_add == rxrd_addr & (lsreg[7]) == 1'b1)
         begin
            lsreg_b7 <= 1'b0 ; // resetting 
         end 
         if (prevrd_lsr == 1'b1 & rd == 1'b0 & (lsreg[7]) == 1'b1)
         begin
            lsreg_b7 <= 1'b0 ; // resetting 
         end 
      end 
   end 

   // Become inactive when the Xmit fifo is completely full
   always @(posedge mr or negedge wr)
   begin
      if (mr == 1'b1)
      begin
         txrdy1 <= 1'b0 ; 
      end
      else
      begin
         if ((fcreg0 == 1'b1 & (fcreg[2]) == 1'b0) & (write_thr == 1'b1 & txfifo_full == 1'b0) & (txrdyn_fifo == 1'b0 & txfifo_value == 15))
         begin
            txrdy1 <= ~txrdy1 ; 
         end 
      end 
   end 

   // There are no characters in the Xmit fifo, it will be active
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         txrdy2 <= 1'b0 ; 
      end
      else
      begin
         if (((fcreg0 == 1'b1 & (fcreg[2]) == 1'b0) & (read_txfifo == 1'b1 & txfifo_empty_int == 1'b0) & (txrdyn_fifo == 1'b1 & txfifo_value == 1)) | (fcreg0 == 1'b1 & (fcreg[2]) == 1'b1 & txrdyn_fifo == 1'b1))
         begin
            // Reseting Xmit Fifo will set TXRDYn
            txrdy2 <= ~txrdy2 ; 
         end 
      end 
   end 

   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         lsreg51_int <= 1'b0 ; 
      end
      else
      begin
         if (fcreg0 == 1'b1 & (fcreg[2]) == 1'b0)
         begin
            if (read_txfifo == 1'b1 & txfifo_empty_int == 1'b0)
            begin
               if (lsreg5 == 1'b0 & txfifo_value == 1)
               begin
                  lsreg51_int <= ~lsreg51_int ; 
               end 
            end 
         end
         else
         begin
            if ((lsreg5 == 1'b0 & (read_txfifo == 1'b1 | (fcreg[2]) == 1'b1)))
            begin
               lsreg51_int <= ~lsreg51_int ; 
            end 
         end 
      end 
   end 

   //--------------------------------------
   // Address pointer for RCVR FIFO write
   // Line status register bits 0 and 2 set
   //--------------------------------------
   always @(posedge reset_rxfifo or posedge rclk)
   begin : RXFIFOwr
      if (reset_rxfifo == 1'b1)
      begin
         rxwr_addr <= 4'b0000 ; //Resetting RCVR FIFO
      end
      else
      begin
         if ((fcreg0 == 1'b1 & (fcreg[1]) == 1'b0) & (write_rxfifo == 1'b1 & rxfifo_full_int == 1'b0))
         begin
            if (rxwr_addr == 4'b1111)
            begin
               rxwr_addr <= 4'b0000 ; 
            end
            else
            begin
               rxwr_addr <= rxwr_addr + 1 ; 
            end 
         end 
         if (fcreg0 == 1'b0)
         begin
            rxwr_addr <= 4'b0000 ; 
         end 
      end 
   end 

   //------------------------------------
   // Address pointer for RCVR FIFO read 
   //------------------------------------
   always @(posedge reset_rxfifo or negedge rd)
   begin : RXFIFOre
      if (reset_rxfifo == 1'b1)
      begin
         rxrd_addr <= 4'b0000 ; //Resetting RCVR FIFO
      end
      else
      begin
         if ((fcreg0 == 1'b1 & (fcreg[1]) == 1'b0) & (write_thr == 1'b1 & rxfifo_empty_int == 1'b0))
         begin
            if (rxrd_addr == 4'b1111)
            begin
               rxrd_addr <= 4'b0000 ; 
            end
            else
            begin
               rxrd_addr <= rxrd_addr + 1 ; 
            end 
         end 
         if (fcreg0 == 1'b0)
         begin
            rxrd_addr <= 4'b0000 ; 
         end 
      end 
   end 

   //-------------------------------------
   // Generate FIFO empty and full signals
   //-------------------------------------
   always @(posedge reset_rxfifo or posedge clk)
   begin
      if (reset_rxfifo == 1'b1)
      begin
         rxfifo_halffull <= 1'b0 ; 
      end
      else
      begin
         if (rxfifo_value > HALFFULLVALUE)
         begin
            rxfifo_halffull <= 1'b1 ; 
         end
         else
         begin
            rxfifo_halffull <= 1'b0 ; 
         end 
      end 
   end 

   always @(rxwr_addr or rxrd_addr or rxfifo_halffull)
   begin
      if (rxwr_addr > rxrd_addr)
      begin
         rxfifo_value <= {1'b0, (rxwr_addr - rxrd_addr)} ; 
      end
      else if ((rxwr_addr == rxrd_addr) & (rxfifo_halffull == 1'b0))
      begin
         rxfifo_value <= 5'b00000 ; 
      end
      else
      begin
         rxfifo_value <= (FIFOMAXVALUE - ({1'b0, rxrd_addr})) + ({1'b0, rxwr_addr}) ; 
      end 
   end 

   always @(rxfifo_value or fcreg0 or lsreg1)
   begin
      if ((rxfifo_value == FIFOMAXVALUE & fcreg0 == 1'b1) | (lsreg1 == 1'b1 & fcreg0 == 1'b0))
      begin
         rxfifo_full_int <= 1'b1 ; 
      end
      else
      begin
         rxfifo_full_int <= 1'b0 ; 
      end 
   end 

   always @(rxfifo_value or fcreg0 or lsreg0)
   begin
      if ((rxfifo_value == 5'b00000 & fcreg0 == 1'b1) | (lsreg0 == 1'b0 & fcreg0 == 1'b0))
      begin
         rxfifo_empty_int <= 1'b1 ; 
      end
      else
      begin
         rxfifo_empty_int <= 1'b0 ; 
      end 
   end 

   //-------------------------------------
   // Address pointer for XMIT FIFO write
   //-------------------------------------
   always @(posedge reset_txfifo or negedge wr)
   begin : TXFIFOwr
      if (reset_txfifo == 1'b1)
      begin
         txwr_addr <= 4'b0000 ; // Resetting XMIT FIFO
      end
      else
      begin
         if ((fcreg0 == 1'b1 & (fcreg[2]) == 1'b0) & (write_thr == 1'b1 & txfifo_full == 1'b0))
         begin
            if (txwr_addr == 4'b1111)
            begin
               txwr_addr <= 4'b0000 ; 
            end
            else
            begin
               txwr_addr <= txwr_addr + 1 ; 
            end 
         end 
         if (fcreg0 == 1'b0)
         begin
            txwr_addr <= 4'b0000 ; 
         end 
      end 
   end 

   //---------------------------------------
   // Address pointer for XMIT FIFO read
   //---------------------------------------
   always @(posedge reset_txfifo or posedge clk)
   begin : TXFIFOre
      if (reset_txfifo == 1'b1)
      begin
         txrd_addr <= 4'b0000 ; // Resetting XMIT FIFO
      end
      else
      begin
         if ((fcreg0 == 1'b1 & (fcreg[2]) == 1'b0) & (read_txfifo == 1'b1 & txfifo_empty_int == 1'b0))
         begin
            if (txrd_addr == 4'b1111)
            begin
               txrd_addr <= 4'b0000 ; 
            end
            else
            begin
               txrd_addr <= txrd_addr + 1 ; 
            end 
         end 
         if (fcreg0 == 1'b0)
         begin
            txrd_addr <= 4'b0000 ; 
         end 
      end 
   end 

   always @(posedge reset_txfifo or posedge clk)
   begin
      if (reset_txfifo == 1'b1)
      begin
         txfifo_halffull <= 1'b0 ; 
      end
      else
      begin
         if (txfifo_value > HALFFULLVALUE)
         begin
            txfifo_halffull <= 1'b1 ; 
         end
         else
         begin
            txfifo_halffull <= 1'b0 ; 
         end 
      end 
   end 

   always @(txwr_addr or txrd_addr or txfifo_halffull)
   begin
      if (txwr_addr > txrd_addr)
      begin
         txfifo_value <= {1'b0, (txwr_addr - txrd_addr)} ; 
      end
      else if ((txwr_addr == txrd_addr) & (txfifo_halffull == 1'b0))
      begin
         txfifo_value <= 5'b00000 ; 
      end
      else
      begin
         txfifo_value <= (FIFOMAXVALUE - ({1'b0, txrd_addr})) + ({1'b0, txwr_addr}) ; 
      end 
   end 

   always @(txfifo_value)
   begin
      if (txfifo_value == FIFOMAXVALUE)
      begin
         txfifo_full <= 1'b1 ; 
      end
      else
      begin
         txfifo_full <= 1'b0 ; 
      end 
   end 

   always @(txfifo_value)
   begin
      if (txfifo_value == 5'b00010)
      begin
         txfifo_2char <= 1'b1 ; 
      end
      else
      begin
         txfifo_2char <= 1'b0 ; 
      end 
   end 

   always @(txfifo_value or fcreg0 or lsreg5)
   begin
      if ((txfifo_value == 5'b00000 & fcreg0 == 1'b1) | (lsreg5 == 1'b1 & fcreg0 == 1'b0))
      begin
         txfifo_empty_int <= 1'b1 ; 
      end
      else
      begin
         txfifo_empty_int <= 1'b0 ; 
      end 
   end 
   assign reset_rxfifo = mr | fcreg[1] ; 
   assign reset_txfifo = mr | fcreg[2] ; 

   //---------------------------------------------------
   // FIFO TYPE MAP (fifo_ram or fifo_reg or fifo_altera)
   //---------------------------------------------------

   uart_fifo u1(.d(d), .rclk(rclk), .wr(wr), .reset_rxfifo(reset_rxfifo), .reset_txfifo(reset_txfifo), .write_thr(write_thr), .rxf(rxf), .rxwr_addr(rxwr_addr), .rxrd_addr(rxrd_addr), .txwr_addr(txwr_addr), .txrd_addr(txrd_addr), .rxfifo_wr(rxfifo_wr), .threg(threg), .rbreg(rbreg), .rbreg_rxf(rbreg_rxf)); 
endmodule