h16550_params.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
   //----------------------------------------------------------------------
   //
   // Copyright (c) 2002-2003 CAST, inc.
   //
   // Please review the terms of the license agreement before using this
   // file.  If you are not an authorized user, please destroy this source
   // code file and notify CAST immediately that you inadvertently RECeived
   // an unauthorized copy.
   //----------------------------------------------------------------------
   //
   //  Project       : H16550 UART
   //
   //  File          : h16550_params.v
   //  Package Name  : h16550_params
   //
   //  Dependencies  : nONE
   //
   //  Description   : Types and Constant VALUEs for H16550
   // 
   //  Designer      : JS
   //
   //  QA Engineer   : JH
   //
   //  Creation Date : 29-January-2002
   //
   //  Last Update   : 16-April-2002
   //
   //  Version       : 2.0V
   //
   //  History       : 1.1 - 02/18/02    VHDL Release
   //                  1.2 - 04/16/02    Performance (size) improved
   //
   //----------------------------------------------------------------------
   // Receiver state machine
   parameter[4:0] WAITING_START = 0; 
   parameter[4:0] REC1_BIT0 = 1; 
   parameter[4:0] REC1_BIT1 = 2; 
   parameter[4:0] REC1_BIT2 = 3; 
   parameter[4:0] REC1_BIT3 = 4; 
   parameter[4:0] REC1_BIT4 = 5; 
   parameter[4:0] REC1_BIT5 = 6; 
   parameter[4:0] REC1_BIT6 = 7; 
   parameter[4:0] REC1_BIT7 = 8; 
   parameter[4:0] REC1_PARITY = 9; 
   parameter[4:0] REC1_STOP0 = 10; 
   parameter[4:0] REC1_STOP1 = 11; 
   parameter[4:0] WAITING2 = 12; 
   parameter[4:0] REC2_BIT0 = 13; 
   parameter[4:0] REC2_BIT1 = 14; 
   parameter[4:0] REC2_BIT2 = 15; 
   parameter[4:0] REC2_BIT3 = 16; 
   parameter[4:0] REC2_BIT4 = 17; 
   parameter[4:0] REC2_BIT5 = 18; 
   parameter[4:0] REC2_BIT6 = 19; 
   parameter[4:0] REC2_BIT7 = 20; 
   parameter[4:0] REC2_PARITY = 21; 
   parameter[4:0] REC2_STOP0 = 22; 
   parameter[4:0] REC2_STOP1 = 23; 
   // Transceiver state machine
   parameter[4:0] WAITING1 = 0; 
   parameter[4:0] SEND_START1 = 1; 
   parameter[4:0] SEND_START2 = 2; 
   parameter[4:0] SEND1_BIT0 = 3; 
   parameter[4:0] SEND1_BIT1 = 4; 
   parameter[4:0] SEND1_BIT2 = 5; 
   parameter[4:0] SEND1_BIT3 = 6; 
   parameter[4:0] SEND1_BIT4 = 7; 
   parameter[4:0] SEND1_BIT5 = 8; 
   parameter[4:0] SEND1_BIT6 = 9; 
   parameter[4:0] SEND1_BIT7 = 10; 
   parameter[4:0] SEND1_PARITY = 11; 
   parameter[4:0] SEND1_STOP0 = 12; 
   parameter[4:0] SEND1_STOP1 = 13; 
   parameter[4:0] SEND2_BIT0 = 14; 
   parameter[4:0] SEND2_BIT1 = 15; 
   parameter[4:0] SEND2_BIT2 = 16; 
   parameter[4:0] SEND2_BIT3 = 17; 
   parameter[4:0] SEND2_BIT4 = 18; 
   parameter[4:0] SEND2_BIT5 = 19; 
   parameter[4:0] SEND2_BIT6 = 20; 
   parameter[4:0] SEND2_BIT7 = 21; 
   parameter[4:0] SEND2_PARITY = 22; 
   parameter[4:0] SEND2_STOP0 = 23; 
   parameter[4:0] SEND2_STOP1 = 24; 
   parameter DATA_WIDTH = 8; 
   parameter ADDR_WIDTH = 3; 
   parameter[15:0] ZERO16 = 16'b0000000000000000; 
   parameter[15:0] ONE16 = 16'b0000000000000001; 
   parameter[15:0] TWO16 = 16'b0000000000000010; 
   parameter[4:0] FIFOMAXVALUE = 5'b10000; // fifo size is 16 byte
   parameter[4:0] HALFFULLVALUE = 5'b01000; // fifo size is 16 byte
   parameter START = 1'b0; 
   parameter STOP = 1'b1;