rxblock.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

                           //rxreg[7] <= sin_org ; 
                           rxf[10] <= sin_org ;
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                           if ((lcreg[3]) == 1'b1)
                           begin
                              state <= REC1_PARITY ; // parity
                           end
                           else
                           begin
                              state <= REC1_STOP0 ; // no parity
                           end 
                        end
               REC1_PARITY :
                        begin
                           state <= REC2_PARITY ; 
                        end
               REC2_PARITY :
                        begin
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                           end 
                           if ((lcreg[5]) == 1'b1)
                           begin
                              // STICK PARITY
                              if (sin_org == ~lcreg[4])
                              begin
                                 pe_pre <= 1'b0 ; 
                              end
                              else
                              begin
                                 pe_pre <= 1'b1 ; 
                              end 
                           end
                           else
                           begin
                              // no STICK
                              if (sin_org == parity)
                              begin
                                 pe_pre <= 1'b0 ; 
                              end
                              else
                              begin
                                 pe_pre <= 1'b1 ; 
                              end 
                           end 
                           state <= REC1_STOP0 ; // stop
                        end
               REC1_STOP0 :
                        begin
                           state <= REC2_STOP0 ; 
                        end
               REC2_STOP0 :
                        begin
                           rxf[0] <= pe_pre ; 
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                           end 
                           if ((rxfifo_full == 1'b1 | ((lsreg[0]) == 1'b1 & (fcreg[0]) == 1'b0)) & (lsreg[1]) == 1'b0 & (lsreg[4]) == 1'b0)
                           begin
                              lsreg11_int <= ~lsreg11_int ; 
                           end 
                           if (sin_org != STOP)
                           begin
                              rxf[1] <= 1'b1 ; 
                              if (not_break_check == 1'b0)
                              begin
                                 state <= WAITING_START ; 
                                 write_rxfifo_int <= 1'b1 ; 
                              end
                              else
                              begin
                                 rxf[2] <= 1'b1 ; 
                              end 
                           end
                           else if ((lcreg[2]) == 1'b0)
                           begin
                              state <= WAITING_START ; // 1 STOP bit
                              write_rxfifo_int <= 1'b1 ; 
                           end
                           else if ((lcreg[1]) == 1'b0 & (lcreg[0]) == 1'b0)
                           begin
                              state <= REC2_STOP1 ; // 1.5 STOP bits
                           end
                           else
                           begin
                              state <= REC1_STOP1 ; // 2 STOP bits
                           end 
                        end
               REC1_STOP1 :
                        begin
                           state <= REC2_STOP1 ; 
                        end
               REC2_STOP1 :
                        begin
                           if (sin_org != STOP)
                           begin
                              rxf[1] <= 1'b1 ; 
                              if (not_break_check == 1'b0)
                              begin
                                 state <= WAITING_START ; 
                                 write_rxfifo_int <= 1'b1 ; 
                              end
                              else
                              begin
                                 rxf[2] <= 1'b1 ; 
                              end 
                           end
                           else
                           begin
                              state <= WAITING_START ; // No more TX data
                              write_rxfifo_int <= 1'b1 ; 
                           end 
                           not_break_check <= 1'b1 ; 
                        end
            endcase 
         end 
         if ((fcreg[1]) == 1'b1 & (lsreg[1]) == 1'b1)
         begin
            lsreg11_int <= ~lsreg11_int ; 
         end 
      end // Reset & Clock
   end 

   //-------------------------
   // Generate RCLK/8 counter
   //-------------------------
   always @(posedge mr or posedge rclk)
   begin
      if (mr == 1'b1)
      begin
         counter8_value <= 3'b000 ; 
      end
      else
      begin
         if (counter8_value == 3'b111)
         begin
            counter8_value <= 3'b000 ; 
         end
         else
         begin
            counter8_value <= counter8_value + 1 ; 
         end 
      end 
   end 

   always @(counter8_value or rxbaud_ref)
   begin
      if (counter8_value == rxbaud_ref)
      begin
         rxbaud <= 1'b1 ; 
      end
      else
      begin
         rxbaud <= 1'b0 ; 
      end 
   end 
   //------------------------------
   // Number of stop bits checking
   //------------------------------
   assign lcreg3210 = lcreg[3:0] ; 

   always @(lcreg3210)
   begin
      case (lcreg3210)
         4'b0000 :
                  begin
                     // 1 STOP BIT  --> 
                     frame_size <= 4'b0110 ; // 5-bit, parity off
                  end
         4'b1000 :
                  begin
                     frame_size <= 4'b0111 ; // 5-bit, parity on
                  end
         4'b0001 :
                  begin
                     frame_size <= 4'b0111 ; // 6-bit, parity off
                  end
         4'b1001 :
                  begin
                     frame_size <= 4'b1000 ; // 6-bit, parity on
                  end
         4'b0010 :
                  begin
                     frame_size <= 4'b1000 ; // 7-bit, parity on
                  end
         4'b1010 :
                  begin
                     frame_size <= 4'b1001 ; // 7-bit, parity on
                  end
         4'b0011 :
                  begin
                     frame_size <= 4'b1001 ; // 8-bit, parity on
                  end
         4'b1011 :
                  begin
                     frame_size <= 4'b1010 ; // 8-bit, parity on
                  end
         4'b0100 :
                  begin
                     // 2 STOP bits  -->
                     frame_size <= 4'b0111 ; // 5-bit, parity off
                  end
         4'b1100 :
                  begin
                     frame_size <= 4'b1000 ; // 5-bit, parity on
                  end
         4'b0101 :
                  begin
                     frame_size <= 4'b1000 ; // 6-bit, parity off
                  end
         4'b1101 :
                  begin
                     frame_size <= 4'b1001 ; // 6-bit, parity on
                  end
         4'b0110 :
                  begin
                     frame_size <= 4'b1001 ; // 7-bit, parity on
                  end
         4'b1110 :
                  begin
                     frame_size <= 4'b1010 ; // 7-bit, parity on
                  end
         4'b0111 :
                  begin
                     frame_size <= 4'b1010 ; // 8-bit, parity on
                  end
         default :
                  begin
                     frame_size <= 4'b1011 ; // 8-bit, parity on
                  end
      endcase 
   end 

   //--------------------------------------
   // Generate Timeout interrupt pre bit 0 
   //--------------------------------------
   always @(posedge mr or posedge rclk)
   begin
      if (mr == 1'b1)
      begin
         topre1 <= 1'b0 ; 
      end
      else
      begin
         if (write_rxfifo_int == 1'b1 & topre_int == 1'b1)
         begin
            topre1 <= ~topre1 ; // resetting pre intterrupt
         end 
      end 
   end 

   //-----------------------------------
   // Generate Timeout interrupt TOBIT0
   //-----------------------------------
   always @(posedge mr or posedge rclk)
   begin
      if (mr == 1'b1)
      begin
         frame_counter0 <= 5'b00000 ; 
         frame_counter1 <= 2'b00 ; 
         topre3 <= 1'b0 ; 
         toint1_int <= 1'b0 ; 
      end
      else
      begin
         if (rxbaud == 1'b1 & rxfifo_empty == 1'b0)
         begin
            if (topre_int == 1'b0)
            begin
               frame_counter0 <= 5'b00000 ; 
               frame_counter1 <= 2'b00 ; 
               topre3 <= ~topre3 ; // setting pre interrupt
            end
            else if (frame_counter0 < ({frame_size, 1'b0}))
            begin
               frame_counter0 <= frame_counter0 + 1 ; 
            end
            else
            begin
               frame_counter0 <= 5'b00000 ; 
               if (frame_counter1 < 3)
               begin
                  frame_counter1 <= frame_counter1 + 1 ; 
               end
               else
               begin
                  frame_counter1 <= 2'b00 ; 
                  if (toint == 1'b0)
                  begin
                     toint1_int <= ~toint1_int ; // Time out interrupt
                  end 
               end 
            end 
         end 
      end 
   end 
endmodule