rxblock.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550 UART
//
//  File          : rxblock.v
//
//  Dependencies  : none 
//
//  Model Type    : Synthesizable Core
//
//  Description   : Receiver block
//
//  Designer      : JU
//
//  QA Engineer   : JH
//
//  Creation Date : 02-January-2002
//
//  Last Update   : 20-June-2003
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/18/02    VHDL Release
//                  1.2 - 04/16/02    Performance (size) improved
//                  2.0 - 06/20/03    Break issue fixed, it will stay
//                                    at stop bits until sin is '1'
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module rxblock (rclk, mr, topre2, toint, rxfifo_full, rxfifo_empty, sin_org, lcreg, fcreg, lsreg, toint1, topre, lsreg11, write_rxfifo, rxf);

   `include "h16550_params.v"

   input rclk; // Receiver Clock
   input mr; // Master Reset
   input topre2; // Time out pre interrupt enable2
   input toint; // Time out interrupt
   input rxfifo_full; // Receiver Fifo Full Flag
   input rxfifo_empty; // Receiver Empty Full Flag
   input sin_org; // Internal Serial input
   input[5:0] lcreg; // Line Control register
   input[5:0] fcreg; // Fifo Control register
   input[6:0] lsreg; // Line Status register
   output toint1; // Time out interrupt enable1
   wire toint1;
   output topre; // Time out pre interrupt
   wire topre;
   output lsreg11; // Line Status register bit 1 enable1
   wire lsreg11;
   output write_rxfifo; // Write Receiver fifo enable
   wire write_rxfifo;
   output[10:0] rxf; 
   reg[10:0] rxf;

   reg[4:0] state; 
   //reg[DATA_WIDTH - 1:0] rxreg; 
   reg[3:0] frame_size; 
   wire[3:0] lcreg3210; 
   reg pe_pre; 
   reg parity; 
   reg rxbaud; 
   reg not_break_check; 
   reg[2:0] counter8_value; 
   reg[2:0] rxbaud_ref; 
   reg topre1; 
   reg topre3; 
   reg[4:0] frame_counter0; 
   reg[1:0] frame_counter1; 
   reg write_rxfifo_int; 
   reg lsreg11_int; 
   wire topre_int; 
   reg toint1_int; 

   assign write_rxfifo = write_rxfifo_int ; 
   assign lsreg11 = lsreg11_int ; 
   assign topre = topre_int ; 
   assign toint1 = toint1_int ; 
   //assign rxf[10:3] = rxreg ; 
   // Timeout first generation
   assign topre_int = topre1 ^ topre2 ^ topre3 ; 

   always @(posedge rclk or posedge mr)
   begin
      if (mr == 1'b1)
      begin
         rxbaud_ref <= 3'b001 ; 
      end
      else
      begin
         if (sin_org == 1'b0 & state == WAITING_START)
         begin
            if (counter8_value == 3'b000)
            begin
               rxbaud_ref <= 3'b111 ; 
            end
            else
            begin
               rxbaud_ref <= counter8_value ; 
            end 
         end 
      end 
   end 

   //---------------
   // STATE MACHINE 
   //---------------
   always @(posedge rclk or posedge mr)
   begin : state_process
      if (mr == 1'b1)
      begin
         state <= WAITING_START ; 
         lsreg11_int <= 1'b0 ; 
         pe_pre <= 1'b0 ; 
         not_break_check <= 1'b0 ; 
         //rxreg <= {1{1'b0}} ; 
         rxf[10:3] <= {8{1'b0}} ;
         rxf[ADDR_WIDTH - 1:0] <= 3'b000 ; 
         write_rxfifo_int <= 1'b0 ; 
         parity <= 1'b0 ; 
      end
      else
      begin
         write_rxfifo_int <= 1'b0 ; 
         if (rxbaud == 1'b1 | (sin_org == 1'b0 & state == WAITING_START))
         begin
            case (state)
               WAITING_START :
                        begin
                           rxf[ADDR_WIDTH - 1:0] <= 3'b000 ; 
                           pe_pre <= 1'b0 ; 
                           parity <= ~lcreg[4] ; 
                           //rxreg <= {1{1'b0}} ; 
                           rxf[10:3] <= {8{1'b0}} ;
                           if (sin_org == START)
                           begin
                              not_break_check <= 1'b1 ; 
                              state <= WAITING2 ; 
                           end
                           else
                           begin
                              state <= WAITING_START ; 
                              not_break_check <= 1'b0 ; 
                           end 
                        end
               WAITING2 :
                        begin
                           state <= REC1_BIT0 ; 
                        end
               REC1_BIT0 :
                        begin
                           state <= REC2_BIT0 ; 
                        end
               REC2_BIT0 :
                        begin
                           state <= REC1_BIT1 ; 
                           //rxreg[0] <= sin_org ; 
                           rxf[3] <= sin_org ;
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                        end
               REC1_BIT1 :
                        begin
                           state <= REC2_BIT1 ; 
                        end
               REC2_BIT1 :
                        begin
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                           state <= REC1_BIT2 ; 
                           //rxreg[1] <= sin_org ; 
                           rxf[4] <= sin_org ;
                        end
               REC1_BIT2 :
                        begin
                           state <= REC2_BIT2 ; 
                        end
               REC2_BIT2 :
                        begin
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                           state <= REC1_BIT3 ; 
                           //rxreg[2] <= sin_org ; 
                           rxf[5] <= sin_org ;
                        end
               REC1_BIT3 :
                        begin
                           state <= REC2_BIT3 ; 
                        end
               REC2_BIT3 :
                        begin
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                           state <= REC1_BIT4 ; 
                           //rxreg[3] <= sin_org ; 
                           rxf[6] <= sin_org ;
                        end
               REC1_BIT4 :
                        begin
                           state <= REC2_BIT4 ; 
                        end
               REC2_BIT4 :
                        begin
                           //rxreg[4] <= sin_org ; 
                           rxf[7] <= sin_org ;
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                           if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b1)
                           begin
                              state <= REC1_PARITY ; // 5 bits, parity
                           end
                           else if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b0)
                           begin
                              state <= REC1_STOP0 ; // 5 bits, no parity
                           end
                           else
                           begin
                              state <= REC1_BIT5 ; // 6 bits or more
                           end 
                        end
               REC1_BIT5 :
                        begin
                           state <= REC2_BIT5 ; 
                        end
               REC2_BIT5 :
                        begin
                           //rxreg[5] <= sin_org ; 
                           rxf[8] <= sin_org ;
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                           if ((lcreg[0]) == 1'b1 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b1)
                           begin
                              state <= REC1_PARITY ; // 6 bits, parity
                           end
                           else if ((lcreg[0]) == 1'b1 & (lcreg[1]) == 1'b0 & (lcreg[3]) == 1'b0)
                           begin
                              state <= REC1_STOP0 ; // 6 bits, no parity
                           end
                           else
                           begin
                              state <= REC1_BIT6 ; // 7 bits or more
                           end 
                        end
               REC1_BIT6 :
                        begin
                           state <= REC2_BIT6 ; 
                        end
               REC2_BIT6 :
                        begin
                           //rxreg[6] <= sin_org ; 
                           rxf[9] <= sin_org ;
                           if (sin_org == 1'b1)
                           begin
                              not_break_check <= 1'b0 ; 
                              parity <= ~parity ; 
                           end 
                           if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b1 & (lcreg[3]) == 1'b1)
                           begin
                              state <= REC1_PARITY ; // 7 bits, parity
                           end
                           else if ((lcreg[0]) == 1'b0 & (lcreg[1]) == 1'b1 & (lcreg[3]) == 1'b0)
                           begin
                              state <= REC1_STOP0 ; // 7 bits, no parity
                           end
                           else
                           begin
                              state <= REC1_BIT7 ; // 8 bits
                           end 
                        end
               REC1_BIT7 :
                        begin
                           state <= REC2_BIT7 ; 
                        end
               REC2_BIT7 :
                        begin