baudgen.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550 UART
//
//  File          : baudgen.v
//
//  Dependencies  : None
//
//  Model Type    : Synthesizable Core
//
//  Description   : Baud Generator
//
//  Designer      : JV
//
//  QA Engineer   : Joram Heilbronner
//
//  Creation Date : 02-January-2002
//
//  Last Update   : 16-April-2002
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/18/02    VHDL Release
//                  1.2 - 04/16/02    Performance (size) improved
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module baudgen (clk, mr, dlreg, dmreg, baudoutn, txbaud);

   `include "h16550_params.v"

   input clk; 
   input mr; 
   input[DATA_WIDTH - 1:0] dlreg; 
   input[DATA_WIDTH - 1:0] dmreg; 
   output baudoutn; 
   wire baudoutn;
   output txbaud; 
   reg txbaud;

   reg[15:0] counter_value; 
   wire[15:0] cmax; 
   reg[2:0] counter8_value; 
   reg baudout_rise; 
   reg baudout_sync; 
   reg baudout_inv; 
   reg baud_clk; 

   assign baudoutn = ~baudout_inv ; 
   // -------------------------------------------------------------------------
   // Generate BAUD GENERATOR counter
   // It will start generate bautout (count counter_value) when
   // both write_dmr and write_dlr are inactive (address is not \"000\" or \"001\")
   //--------------------------------------------------------------------------
   assign cmax = (({dmreg, dlreg}) - 16'b0000000000000001) ; 

   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         counter_value <= TWO16 ; 
      end
      else
      begin
         if ((counter_value >= cmax) & (({dmreg, dlreg[7:1]}) != ZERO16[15:1]))
         begin
            counter_value <= ZERO16 ; 
         end
         else
         begin
            counter_value <= counter_value + 16'b0000000000000001 ; 
         end 
      end 
   end 

   //-----------------------------------------------
   // Generate interrupts and priorities
   //-----------------------------------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         baudout_sync <= 1'b0 ; 
         baudout_rise <= 1'b0 ; 
      end
      else
      begin
         if (({dmreg, dlreg[7:1]}) == ZERO16[15:1])
         begin
            // N = 1 or 0
            baudout_sync <= 1'b0 ; 
            baudout_rise <= 1'b1 ; 
         end
         else
         begin
            // N >= 2
            case (counter_value)
               ONE16 :
                        begin
                           baudout_sync <= 1'b0 ; 
                           baudout_rise <= 1'b1 ; 
                        end
               TWO16 :
                        begin
                           baudout_rise <= 1'b0 ; 
                           baudout_sync <= 1'b0 ; 
                        end
               default :
                        begin
                           baudout_sync <= 1'b1 ; 
                           baudout_rise <= 1'b0 ; 
                        end
            endcase 
         end 
      end 
   end 

   always @(dmreg or dlreg)
   begin
      if (({dmreg, dlreg[7:1]}) == ZERO16[15:1])
      begin
         // N = 1 or 0
         baud_clk <= 1'b1 ; 
      end
      else
      begin
         baud_clk <= 1'b0 ; 
      end 
   end 

   always @(clk or baud_clk or baudout_sync)
   begin
      if (baud_clk == 1'b1)
      begin
         baudout_inv <= clk ; 
      end
      else
      begin
         baudout_inv <= ~baudout_sync ; 
      end 
   end 

   //-----------------------------
   // Generate BAUDOUT/16 counter 
   //-----------------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         counter8_value <= 3'b000 ; 
         txbaud <= 1'b0 ; 
      end
      else
      begin
         txbaud <= 1'b0 ; 
         if (baudout_rise == 1'b1)
         begin
            if (counter8_value == 3'b111)
            begin
               counter8_value <= 3'b000 ; 
            end
            else
            begin
               counter8_value <= counter8_value + 1 ; 
            end 
            if (counter8_value == 3'b000)
            begin
               txbaud <= 1'b1 ; 
            end 
         end 
      end 
   end 
endmodule