intcontrol.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550 UART
//
//  File          : intcontrol.v
//
//  Dependencies  : none 
//
//  Model Type    : Synthesizable Core
//
//  Description   : interrupt controller
//
//  Designer      : JV
//
//  QA Engineer   : JH
//
//  Creation Date : 02-January-2002
//
//  Last Update   : 20-June-2003
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/18/02    VHDL Release
//                  1.2 - 04/16/02    Performance (size) improved
//                  2.0 - 06/20/03    Add thrint5
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module intcontrol (rd, wr, mr, toint1, topre, at_trig_level, read_iir, write_thr, thrint1, thrint4, thrint5, rbrint1, lsreg, msreg, iereg, toint, topre2, rbrint, thrint, intr, iireg);

   `include "h16550_params.v"

   input rd; // Read Enable
   input wr; // Write Enable
   input mr; // Master Reset
   input toint1; // TimeOut interrupt 1 enable
   input topre; // TimeOut pre interrupt
   input at_trig_level; // At trigger level flag
   input read_iir; // Read Interrupt Status Register Enable
   input write_thr; // Write Transmitter Holding Register Enable
   input thrint1; // Transmitter Holding Register Empty interrupt1
   input thrint4; // Transmitter Holding Register Empty interrupt4
   input thrint5; // Transmitter Holding Register Empty interrupt5 (set ier1)
   input rbrint1; // Received Data interrupt1
   input[DATA_WIDTH - 1:0] lsreg; // Line status register
   input[3:0] msreg; // Modem status register
   input[3:0] iereg; // Interrupt Enable register
   output toint; // Timeout interrupt enable
   wire toint;
   output topre2; // Timeout pre interrupt enable2
   wire topre2;
   output rbrint; // Received Data interrupt
   wire rbrint;
   output thrint; // Transmitter Holding register interrupt
   wire thrint;
   output intr; // Interrupt
   reg intr;
   output[3:0] iireg; 
   reg[3:0] iireg;

   reg interrupt0; 
   reg interrupt2; 
   reg interrupt3; 
   reg interrupt1; 
   reg interrupt1f; 
   reg rbrint2; 
   reg thrint2; 
   reg thrint3; 
   reg toint2; 
   wire toint_int; 
   reg topre2_int; 
   wire rbrint_int; 
   wire thrint_int; 

   assign toint = toint_int ; 
   assign topre2 = topre2_int ; 
   assign rbrint = rbrint_int ; 
   assign thrint = thrint_int ; 
   assign toint_int = toint1 ^ toint2 ; 
   assign rbrint_int = rbrint1 ^ rbrint2 ; 
   assign thrint_int = thrint1 ^ thrint2 ^ thrint3 ^ thrint4 ^ thrint5 ; 

   //-----------------------------------------
   // Generate receiver line status interrupt 
   //-----------------------------------------
   always @(lsreg or iereg)
   begin
      // OE              PE              FE              BI
      if (((lsreg[1]) == 1'b1 | (lsreg[2]) == 1'b1 | (lsreg[3]) == 1'b1 | (lsreg[4]) == 1'b1) & (iereg[2]) == 1'b1)
      begin
         interrupt0 <= 1'b1 ; 
      end
      else
      begin
         interrupt0 <= 1'b0 ; 
      end 
   end 

   always @(posedge mr or negedge rd)
   begin
      if (mr == 1'b1)
      begin
         rbrint2 <= 1'b0 ; 
      end
      else
      begin
         if (write_thr == 1'b1 & at_trig_level == 1'b1)
         begin
            rbrint2 <= rbrint1 ; 
         end 
      end 
   end 

   always @(posedge mr or negedge rd)
   begin
      if (mr == 1'b1)
      begin
         topre2_int <= 1'b0 ; 
         toint2 <= 1'b0 ; 
      end
      else
      begin
         if (write_thr == 1'b1 & topre == 1'b1)
         begin
            topre2_int <= ~topre2_int ; 
         end 
         if (write_thr == 1'b1 & toint_int == 1'b1)
         begin
            toint2 <= ~toint2 ; 
         end 
      end 
   end 

   always @(rbrint_int or toint_int or iereg)
   begin
      if (rbrint_int == 1'b1 & (iereg[0]) == 1'b1)
      begin
         interrupt1 <= 1'b1 ; 
      end
      else
      begin
         interrupt1 <= 1'b0 ; 
      end 
      if (toint_int == 1'b1 & (iereg[0]) == 1'b1)
      begin
         interrupt1f <= 1'b1 ; 
      end
      else
      begin
         interrupt1f <= 1'b0 ; 
      end 
   end 

   always @(posedge mr or negedge rd)
   begin
      if (mr == 1'b1)
      begin
         thrint2 <= 1'b0 ; 
      end
      else
      begin
         if (read_iir == 1'b1 & thrint_int == 1'b1)
         begin
            thrint2 <= ~thrint2 ; 
         end 
      end 
   end 

   always @(posedge mr or negedge wr)
   begin
      if (mr == 1'b1)
      begin
         thrint3 <= 1'b0 ; 
      end
      else
      begin
         if (write_thr == 1'b1 & thrint_int == 1'b1)
         begin
            thrint3 <= ~thrint3 ; 
         end 
      end 
   end 

   always @(thrint_int or iereg)
   begin
      if (thrint_int == 1'b1 & (iereg[1]) == 1'b1)
      begin
         interrupt2 <= 1'b1 ; 
      end
      else
      begin
         interrupt2 <= 1'b0 ; 
      end 
   end 

   //-----------------------------------------
   // Generate receiver line status interrupt
   //-----------------------------------------
   always @(msreg or iereg)
   begin
      // CTS            DSR              RI              DCD
      if (((msreg[0]) == 1'b1 | (msreg[1]) == 1'b1 | (msreg[2]) == 1'b1 | (msreg[3]) == 1'b1) & (iereg[3]) == 1'b1)
      begin
         interrupt3 <= 1'b1 ; 
      end
      else
      begin
         interrupt3 <= 1'b0 ; 
      end 
   end 

   //-----------------------------------
   // Generate interrupts and priorities
   //-----------------------------------
   always @(interrupt0 or interrupt1 or interrupt1f or interrupt2 or interrupt3)
   begin
      if (interrupt0 == 1'b1 | interrupt1 == 1'b1 | interrupt1f == 1'b1 | interrupt2 == 1'b1 | interrupt3 == 1'b1)
      begin
         intr <= 1'b1 ; 
      end
      else
      begin
         intr <= 1'b0 ; 
      end 
   end 

   always @(interrupt0 or interrupt1 or interrupt1f or interrupt2 or interrupt3)
   begin
      if (interrupt0 == 1'b1)
      begin
         // highest
         iireg <= 4'b0110 ; 
      end
      else if (interrupt1 == 1'b1)
      begin
         // 2.
         iireg <= 4'b0100 ; 
      end
      else if (interrupt1f == 1'b1)
      begin
         // 2.
         iireg <= 4'b1100 ; 
      end
      else if (interrupt2 == 1'b1)
      begin
         // 3.
         iireg <= 4'b0010 ; 
      end
      else if (interrupt3 == 1'b1)
      begin
         // 4.
         iireg <= 4'b0000 ; 
      end
      else
      begin
         iireg <= 4'b0001 ; 
      end 
   end 
endmodule