exemplar_altera.tcl

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

clean_all
set START_SYN_TIME [clock seconds]

#if not set then set
if { $EFFORT == "" } {set EFFORT standard}
if { $MODE == "" } {set MODE area}
if { $HIERARCHY == "" } {set HIERARCHY auto}
if { $BOUNDARY == "" } {set BOUNDARY -boundary}
if { $CHIPMACRO == "" } {set CHIPMACRO -chip}

if { $LIBRARY == "" } { puts "ERROR:ERROR:ERROR: LIBRARY needs to be set" }

# StateMachine encoding style  Gray Binary OneHot TwoHot Random Auto
if { ${encoding} == ""} {set encoding OneHot}

# The timing constraints of a design need to be applied after the design is read in.
# We are using a TCL procedure here so that we can apply the constraints later in the script

puts "\nSTART: REPORTING\n"

proc TIMING_CONSTRAINTS {} {

global TOP GLOBAL_PERIOD

puts "\nAssign constraints to the design $TOP: define clocks, buffers & PIN allocations etc\n"

# Global constraints in nana seconds, the slowest requirements in your system

set register2register $GLOBAL_PERIOD
set input2register $GLOBAL_PERIOD
set register2output $GLOBAL_PERIOD
set input2output $GLOBAL_PERIOD


#Specify Clock setup/hold constraints

puts "Reporting External Clocks"
foreach CLOCK [all_clocks] {
   set FANOUT [llength [list_connection -net $CLOCK -hierarchical -direction DRIVEN]]
   set FAOUNT [expr ${FANOUT}/2];puts "EXTERNAL PORT CLOCK : fanout $FANOUT $CLOCK"
   set_clock -port -name "$CLOCK" -clock_cycle $GLOBAL_PERIOD -pulse_width [expr $GLOBAL_PERIOD / 2]
}

puts "Reporting Internal Clocks"
# Internal Clocks
foreach CLOCK [all_clocks -internal] {
   set FANOUT [llength [list_connection -net $CLOCK -hierarchical -direction DRIVEN]]
   set FANOUT [expr $FANOUT/2];
   puts "INTERNAL CLOCK: fanout $FANOUT $CLOCK"
   set_clock -port -name "$CLOCK" -clock_cycle $GLOBAL_PERIOD -pulse_width [expr $GLOBAL_PERIOD / 2]
   set_attribute -net $CLOCK -name _CLOCK -value 1
}

puts "Reporting FANOUT"
proc LIST_FANOUT {max} {
 foreach view [dfs] {
  foreach NET [list_design $view -nets] {
   set FANOUT [llength [list_connection -net $NET -hierarchical -direction DRIVEN]]
   #set FANOUT [expr $FANOUT/2]
    if {$FANOUT > $max} {
	puts "NET: fanout $FANOUT $NET"
    }
  }
 }
}
LIST_FANOUT 50


# Define Pin/Buffer(Global Buffers) constraints

#set_attribute .work.stopwatch.rtl.reset_button -name PAD -value BUFGP -port

#ASSIGN_PIN clk P1
#ASSIGN_PIN global_reset P2
}

##################### Start Technology Selection ######################

# Your Technology library and part need to be defined

###"Setting up the Part for ACEX device"
#puts "Setting up the Part"
#set LIBRARY acex1
#set part ep1k100qc208
#set process 1

load_library $LIBRARY

##################### End Technology Selection ######################


#
# Files List stored in a file called "filelist.txt"
#
set HDL_LIBRARY temp
set LIST [list]

set fileId [open filelist.txt r]
set LIST [list]
while {[gets $fileId line] >=0} { 
   if {[regexp  {^START HDL_LIBRARY ([^ ]+)} $line TMP HDL_LIBRARY] == 1} {set LIST [list];continue}
   if {[regexp {^(#.*|$)} $line ] == 1} {continue}
   if {[regexp  {^END HDL_LIBRARY} $line ] == 1} {
      puts "Loading files into HDL Library : $HDL_LIBRARY"
      puts "Files: $LIST"
      read -technology $LIBRARY -work $HDL_LIBRARY -format Verilog $LIST
      continue
   }
   lappend LIST $line 
   #puts $line
}

close $fileId


#
regexp -nocase {([^ ]+)\.([^ \.]+)\.([^ \.]+)} [present_design] TOP WORK ENTITY ARCH
#

pre_optimize -common_logic -unused_logic -boundary -xor_comparator_optimize 
pre_optimize -extract 

write -format xdb ${ENTITY}_pre_synthesis.xdb

puts "\nSTART: Define Contraints\n"
TIMING_CONSTRAINTS
puts "\nEND: Define Contraints\n"


puts "\nSTART: Optimizing $TOP with MODE:$MODE EFFORT:$EFFORT HEIRHARCY:$HIERARCHY\n"

set M(auto) AU ; set M(area) A ; set M(delay) D
set H(preserve) P ; set H(flatten) F ; set H(auto) AU
set E(standard) S ; set E(quick) Q 

set FILENAME altera/$ALTCMD_TECH/${ENTITY}_AREA_DELAY_$M($MODE)_EFFORT_$E($EFFORT)_HIERARCHY_$H($HIERARCHY)
if { $CHIPMACRO == "-chip" } { set FILENAME ${FILENAME}_pad }


optimize $TOP -target $LIBRARY -effort $EFFORT -hierarchy $HIERARCHY ${BOUNDARY} $CHIPMACRO -$MODE
#Optional
#optimize_timing $TOP 


proc WRITE_RLOC_RANGE_UCF {INSTANCE RLOC_RANGE UCF} {

# Start of Constraints extracted by Floorplanner from the Design
#AREA_GROUP "AG_ mulloc" RANGE = SLICE_X0Y5:SLICE_X7Y0 ;
#INST "reg_pdt_int(2)(15)" AREA_GROUP = "AG_ mulloc" ;
#...
		file delete ${UCF}.ucf
		if [catch {open ${UCF}.ucf a+} STREAM]  {} else {
			puts "\nWriting ${UCF}.ucf file for [present_design]\n"
			set AREA_GROUP RLOC_RANGE
			puts $STREAM "AREA_GROUP \"${AREA_GROUP}\" RANGE = SLICE_X0Y5:SLICE_X7Y0 ;"
			puts $STREAM "AREA_GROUP ${AREA_GROUP} COMPRESSION = 1;"
			foreach INST [list_design -instances -short $INSTANCE ] {
				puts $STREAM "INST \"$INST\" AREA_GROUP = \"${AREA_GROUP}\" ;"
			}
		}
		close $STREAM
} 

set edif_array_range_extraction_style %s(%d:%d)
set hdl_array_name_style %s(%d) 

auto_write ${FILENAME}.xdb
auto_write ${FILENAME}.edf

puts "\nEND: Optimizing $TOP\n"

proc PRINT_FILE {FILE} { 
   if [catch {open $FILE r} STREAM]  {} else { 
      while {[gets $STREAM LINE] >= 0} { 
         puts $LINE 
      }
   }
   close $STREAM 
} 

puts "\nSTART: REPORTING\n"

set FILE ${FILENAME}_A.txt
report_area $FILE -cell_usage -all_leafs
PRINT_FILE $FILE

set FILE ${FILENAME}_T.txt
report_delay $FILE -num_paths 1 -critical_paths -clock_frequency
PRINT_FILE $FILE

set END_SYN_TIME [clock seconds]
set TIME_RUN [expr $END_SYN_TIME - $START_SYN_TIME]
puts "\nEND: REPORTING\n"

puts "Run Time [clock format $TIME_RUN -format {%H h %M min %S sec} -gmt 1]"