exemplar_xilinx.tcl

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

clean_all
set START_SYN_TIME [clock seconds]

#if not set then set
if { $EFFORT == "" } {set EFFORT standard}
if { $MODE == "" } {set MODE area}
if { $HIERARCHY == "" } {set HIERARCHY auto}
if { $BOUNDARY == "" } {set BOUNDARY -boundary}
if { $CHIPMACRO == "" } {set CHIPMACRO -chip}
if { $XILCMD_TECH == "" } {set XILCMD_TECH ""}
if { $XILCMD_PART == "" } {set XILCMD_PART ""}

if { $LIBRARY == "" } { puts "ERROR:ERROR:ERROR: LIBRARY needs to be set" }

# StateMachine encoding style  Gray Binary OneHot TwoHot Random Auto
if { ${encoding} == ""} {set encoding OneHot}

puts "test"
proc XILRUN {FILE} {
   global XILCMD_TECH XILCMD_PART ENTITY
   set STREAM [open $FILE w]
   puts $STREAM "#!/bin/csh -f"
   puts $STREAM "ngdbuild -p $XILCMD_PART -uc $ENTITY.ucf $ENTITY.edf $ENTITY.ngd"
   puts $STREAM "map -p $XILCMD_PART -c 10 -cm speed -o map.ncd $ENTITY.ngd $ENTITY.pcf"
   puts $STREAM "par -w -ol 5 map.ncd $ENTITY.ncd $ENTITY.pcf"
   puts $STREAM "trce $ENTITY.ncd $ENTITY.pcf -e 3 -o $ENTITY.twr -xml $ENTITY.twx"
   puts $STREAM "ngdanno $ENTITY.ncd map.ngm"
   puts $STREAM "ngd2vhdl -w -r $ENTITY.nga"
   puts $STREAM "move $ENTITY.sdf ${ENTITY}_vhd.sdf"
   puts $STREAM "ngd2ver -w -r $ENTITY.nga"
   puts $STREAM "move $ENTITY.sdf ${ENTITY}_v.sdf"
   close $STREAM
} 
puts "\nSTART: REPORTING\n"


proc TIMING_CONSTRAINTS {} {

global TOP GLOBAL_PERIOD

puts "\nAssign constraints to the design $TOP: define clocks, buffers, etc\n"

# Global constraints in nana seconds, the slowest requirements in your system

set register2register $GLOBAL_PERIOD
set input2register $GLOBAL_PERIOD
set register2output $GLOBAL_PERIOD
set input2output $GLOBAL_PERIOD


#Specify Clock setup/hold constraints
puts "Reporting External Clocks"
foreach CLOCK [all_clocks] {
   set FANOUT [llength [list_connection -net $CLOCK -hierarchical -direction DRIVEN]]
   set FAOUNT [expr ${FANOUT}/2];puts "EXTERNAL PORT CLOCK : fanout $FANOUT $CLOCK"
   set_clock -port -name "$CLOCK" -clock_cycle $GLOBAL_PERIOD -pulse_width [expr $GLOBAL_PERIOD / 2]
}

puts "Reporting Internal Clocks"
foreach CLOCK [all_clocks -internal] {
   set FANOUT [llength [list_connection -net $CLOCK -hierarchical -direction DRIVEN]]
   set FANOUT [expr $FANOUT/2];
   puts "INTERNAL CLOCK: fanout $FANOUT $CLOCK"
   set_clock -port -name "$CLOCK" -clock_cycle $GLOBAL_PERIOD -pulse_width [expr $GLOBAL_PERIOD / 2]
   set_attribute -net $CLOCK -name _CLOCK -value 1
}

puts "Reporting FANOUT"
proc LIST_FANOUT {max} {
 foreach view [dfs] {
   foreach NET [list_design $view -nets] {
    set FANOUT [llength [list_connection -net $NET -hierarchical -direction DRIVEN]]
    #set FANOUT [expr $FANOUT/2]
    if {$FANOUT > $max} {
	puts "NET: fanout $FANOUT $NET"
     }
   }
  }
}
LIST_FANOUT 50

}

##################### Start Technology Selection ######################

# Your Technology library and part need to be defined before including this!

###"Setting up the Part Spartan Devices"
#puts "Setting up the Part"
#set LIBRARY xis
#set part s40bg256
#set process 4
#set wire_table s40-4_avg

load_library $LIBRARY

##################### End Technology Selection ######################

#
# Files List stored in a file called "filelist.txt"
#
set HDL_LIBRARY temp
set LIST [list]

set fileId [open filelist.txt r]
set LIST [list]
while {[gets $fileId line] >=0} { 
   if {[regexp  {^START HDL_LIBRARY ([^ ]+)} $line TMP HDL_LIBRARY] == 1} {set LIST [list];continue}
   if {[regexp {^(#.*|$)} $line ] == 1} {continue}
   if {[regexp  {^END HDL_LIBRARY} $line ] == 1} {
      puts "Loading files into HDL Library : $HDL_LIBRARY"
      puts "Files: $LIST"
		 
      read -technology $LIBRARY -work $HDL_LIBRARY -format Verilog $LIST
      continue
   }
   lappend LIST $line 
   #puts $line
}

close $fileId

regexp -nocase {([^ ]+)\.([^ \.]+)\.([^ \.]+)} [present_design] TOP WORK ENTITY ARCH
#

pre_optimize -common_logic -unused_logic -boundary -xor_comparator_optimize 
pre_optimize -extract 

write -format xdb ${ENTITY}_pre_synthesis.xdb

puts "\nSTART: Define Contraints\n"
TIMING_CONSTRAINTS
puts "\nEND: Define Contraints\n"

puts "\nSTART: Optimizing $TOP with MODE:$MODE EFFORT:$EFFORT HEIRHARCY:$HIERARCHY\n"

set M(auto) AU ; set M(area) A ; set M(delay) D
set H(preserve) P ; set H(flatten) F ; set H(auto) AU
set E(standard) S ; set E(quick) Q 

#system dependent exec "mkdir ilinx"
#system dependent exec "mkdir $XILCMD_TECH"
set FILENAME xilinx/$XILCMD_TECH/${ENTITY}_MODE_$M($MODE)_EFFORT_$E($EFFORT)_HIERARCHY_$H($HIERARCHY)_${LIBRARY}
if { $CHIPMACRO == "-chip" } { set FILENAME ${FILENAME}_pad }

puts "Writing xilrun.cmd"
set FILE ${XILCMD_TECH}_xilrun.cmd
XILRUN $FILE 

optimize $TOP -target $LIBRARY -effort $EFFORT -hierarchy $HIERARCHY ${BOUNDARY} $CHIPMACRO -$MODE
#Optional
#optimize_timing $TOP 


set edif_array_range_extraction_style %s(%d:%d)
set hdl_array_name_style %s(%d) 

auto_write ${FILENAME}.xdb
auto_write ${FILENAME}.edf

puts "\nEND: Optimizing $TOP\n"

proc PRINT_FILE {FILE} { 
   if [catch {open $FILE r} STREAM]  {} else { 
      while {[gets $STREAM LINE] >= 0} { 
         puts $LINE 
      }
   }
   close $STREAM 
} 

puts "\nSTART: REPORTING\n"

set FILE ${FILENAME}_A.txt
report_area $FILE -cell_usage -all_leafs
PRINT_FILE $FILE

set FILE ${FILENAME}_T.txt
report_delay $FILE -num_paths 1 -critical_paths -clock_frequency
PRINT_FILE $FILE

set END_SYN_TIME [clock seconds]
set TIME_RUN [expr $END_SYN_TIME - $START_SYN_TIME]
puts "\nEND: REPORTING\n"


puts "Run Time [clock format $TIME_RUN -format {%H h %M min %S sec} -gmt 1]"