synopsys.scr

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

/*----------------------------------------------------------------------
--
-- Copyright (c) 2002-2003 CAST, inc.
--
-- Please review the terms of the license agreement before using this
-- file.  If you are not an authorized user, please destroy this source
-- code file and notify CAST immediately that you inadvertently received
-- an unauthorized copy.
------------------------------------------------------------------------
--
--  Project       : H16550
--
--  Description   : H16550 UART with FIFO
--
--  File          : synopsys.scr 
--
--  Purpose       : Sample Synopsys synthesis script
--
--  Designer      : NJS
--
--  QA Engineer   : JH
--
--  Creation Date : 29-January-2002
--
--  Last Update   : 11-April-2002
--
--  Version       : 2.0
--
------------------------------------------------------------------------*/

   company  = "CAST, Inc"

   TOP = h16550

/* ================================================= */
/* Source files needed                               */
/* ================================================= */

   /*source_files     = { h16550_params.v \ */
   source_files     = { baudgen.v \
                        uart_fifo.v \
                        fifoctrl.v \
                        intcontrol.v \
                        rwcontrol.v \
                        uart_reg.v \
                        rxblock.v \
                        txblock.v \
                        h16550.v} 

/* ================================================= */
/* List of pre compiled modules                      */
/* ================================================= */

   precomp_modules  = { }

/* ================================================= */
/* Directories location                              */
/* ================================================= */

   source_dir       = "../src/"
   db_dir           = "./db/"
   net_dir          = "./nets/"
   report_dir       = "./reports/"

/* ================================================= */
/* Create Directories                                */
/* ================================================= */

   sh mkdir db_dir
   sh mkdir net_dir
   sh mkdir report_dir
   sh mkdir work 
 
/* ================================================= */
/* Clock Timing Specifications                       */
/* ================================================= */
   clock_nets           = {clk rclk rd wr}
   main_clock           = clk  

   def_clock_period     = 100 
   def_clock_wave       = {0 50}

   /*cond                 =   */
   /*net_max_fanout       =   */
   /*def_input_drive      =   */
   def_input_time_min   = 0.5
   def_input_time_max   = 1
   /*def_input_max_fanout =   */
   /*def_output_load      =   */
   def_output_time_min  = -0.5
   def_output_time_max  = 20

/* ================================================= */
/* Analyze and Elaborate the design file and specify */
/* the design file format.			     */
/* ================================================= */

   foreach (file, source_files) {
       analyze -format verilog source_dir + file
   }
   elaborate TOP

/* ================================================= */
/* Read all pre compiled modules and apply           */
/* dont_touch attributes                             */
/* ================================================= */

   foreach (module, precomp_modules) {
      remove_design module -hierarchy
      read -format db db_dir + module + "_compiled.db"
      if (dc_shell_status == 0) {
         echo "Error: Error in loading precompiled db files"
         exit
      }
      dont_touch module
   }

/* ================================================= */
/* Set the current design to the top level.          */
/* ================================================= */

   current_design TOP
   uniquify

/* ================================================= */
/* Set the synthesis design constraints.             */  
/* ================================================= */

   /*set_operating_conditions cond
   set_max_fanout net_max_fanout find(design)
   set_drive def_input_drive all_inputs()
   set_max_fanout def_input_max_fanout all_inputs()
   set_load def_output_load all_outputs()*/

   foreach (clock, clock_nets) {
     create_clock clock -period def_clock_period -waveform def_clock_wave
     if (dc_shell_status == 0) {
       echo "Error: Can't set clock" + clock
       exit
     }
     set_drive 0 clock                   /* prevents buffering on clock net */
     /*set_dont_touch_network clock*/ 	

     set_input_delay -clock clock -max def_input_time_max find (port all_inputs() - clock_nets)
     set_input_delay -clock clock -min def_input_time_min find (port all_inputs() - clock_nets)
     set_output_delay -clock clock -max def_output_time_max find (port all_outputs())
     set_output_delay -clock clock -min def_output_time_min find (port all_outputs())

   }

   /*set_input_delay def_input_time -clock main_clock all_inputs()
   set_output_delay def_output_time -clock main_clock all_outputs()*/

   set_max_area 0

   compile -map_effort high 

/* ================================================= */
/* Write the design report files.                    */
/* ================================================= */

   check_design > report_dir + TOP + ".chk_des"

   report_area > report_dir + TOP  + ".rep"
   report_cell >> report_dir + TOP  + ".rep"
   report_clock >> report_dir + TOP + ".rep"
   report_timing -max 40 >> report_dir + TOP + ".rep"

   report_constraints -all_violators -verbose > report_dir + TOP + ".violate"

/* ================================================= */
/* Write out the design                              */
/* ================================================= */

   write -format db -hierarchy -output db_dir + TOP + ".db"
   write -format vhdl -hierarchy -output net_dir + TOP + "_gate.vhd"
   write -format verilog -hierarchy -output net_dir + TOP + "_gate.v"
   /*write -format edif -hierarchy -output db_dir + TOP + ".edf"*/

/* ================================================= */
/* Exit the Compiler                                 */
/* ================================================= */

   exit