h16550tb7.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

   end

   h16550w u1 (.a(a), .adsn(ads), .cs0(cs), .cs1(vcc), .cs2n(gnd), .wr(wr),
   .rd(rd), .mr(mr), .clk(clk), .rclk(rclk), .sin(sin), .ctsn(cts), .dsrn(dsr), .dcdn(dcd),
   .rin(ri), .ddis(ddis), .baudoutn(baudout), .sout(sout), .rtsn(rts), .dtrn(dtr),
   .out1n(out1), .out2n(out2), .intr(intr), .rxrdyn(rxrdyn), .txrdyn(txrdyn),
   .dout(dout[7:0]), .din(din[7:0])); 

   //-------------------------------------------------   
   // Infinite clock generator
   //-------------------------------------------------
   always @(baudout)
   begin 
      rclk <= baudout ;
   end

   //-------------------------------------------------
   // Asynchronous reset 
   //-------------------------------------------------
   always 
   begin
      #50; 
      mr <= 1'b1 ; 
      #230; 
      mr <= 1'b0 ; 
      @(posedge test_done); 
      mr <= 1'b1 ; 
      #200; 
      mr <= 1'b0 ; 
      forever #100000; 
   end 

   always 
   begin : clk_stim
      forever
      begin
         #(period / 2); 
         clk <= ~clk ; 
         if (test_done == 1'b1)
         begin
            clk <= ~clk ;
            $display("TEST COMPLETE");
            if (errors == 0)
            begin
               $display("There were no errors");
            end
            else
            begin
               $display("There were %d Errors", errors);
            end
            forever #100000; 
         end 
      end 
   end 

   always @(sout or frame_error)
   begin
      if (frame_error)
      begin
         sin <= #2 ~(sout) ; 
      end
      else
      begin
         sin <= #2 sout ; 
      end 
   end 

   always 
   begin : full_test
      din <= 8'b00000000 ; 
      rd <= 1'b0 ; 
      wr <= 1'b0 ; 
      cs <= 1'b0 ; 
      ads <= 1'b0 ; 
      a <= 3'b000 ; 
      @(posedge clk); 
      #cpu_tpd; 
      if (dtr == 1'b1)
      begin
         $display("\n  DTR output during RESET  OK"); 
      end
      else
      begin
         $display("\n  DTR output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      if (rts == 1'b1)
      begin
         $display("  RTS output during RESET  OK"); 
      end
      else
      begin
         $display("  RTS output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      if (out1 == 1'b1)
      begin
         $display("  OUT1 output during RESET  OK"); 
      end
      else
      begin
         $display("  OUT1 output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      if (out2 == 1'b1)
      begin
         $display("  OUT2 output during RESET  OK"); 
      end
      else
      begin
         $display("  OUT2 output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      @(negedge mr); 
      wait_n_cycle(10); 
      //--------------------------------------------------------------------
      // The first action is to write an initial value to all necessary registers
      // then send three bytes with the second one having a frame error.  Then
      // read the IIR and LSR registers.  Finally, place the device in 16450 mode.
      //--------------------------------------------------------------------
      $display("\n    MPU writes initial registers");
      // Set DLAB and make the word 8 bits 2 stop bits and no parity
      // LINE Control register
      cpu_write(8'b10000111, lcradd, 1'b0); 
      // Set Devisor registers to 02
      // Devisor Latch (LSB) Register
      cpu_write(8'b00000010, dlradd, 1'b1); 
      // Devisor registers to 02
      // Devisor Latch (MSB) Register
      cpu_write(8'b00000000, dmradd, 1'b1); 
      // Reset DLAB and make the word 8 bits 2 stop bits and no parity
      // LINE Control register
      cpu_write(8'b00000111, lcradd, 1'b0); 
      $display("\n    Enable Interrupts");
      // Enable Line Status Interrupt
      // IE register
      cpu_write(8'b00000100, ieradd, 1'b0); 
      // Set receiver trigger at 8 (we don\'t want to interupt for
      // receiver fifo, rather for the framing error) and enable FIFOs
      // FC register
      cpu_write(8'b10000001, fcradd, 1'b0); 
      $display("\n  Write the transmission register and wait for the transmissions\n");
      // Send 55 first
      // Transmitter Holding register
      cpu_write(8'b01010101, thradd, 1'b0); 
      // Send AA next
      // Transmitter Holding register
      cpu_write(8'b10101010, thradd, 1'b0); 
      // Send CC last
      // Transmitter Holding register
      cpu_write(8'b11001100, thradd, 1'b0); 
      $display("\n  Waiting\n"); 
      wait_n_cycle(299); 
      frame_error <= 1'b1 ; 
      wait_n_cycle(32); 
      frame_error <= 1'b0 ; 
      wait_n_cycle(710); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // Should have Error in RCVR FIFO, Transmitter Holding Register 
      // Framing Error and Data Ready
      // Line Status Register
      cpu_read(lsradd, 8'b10101001, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // Disable FIFOs and clear them
      // FC register
      cpu_write(8'b00000000, fcradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // Enable THR Empty Interrupt
      // IE register
      cpu_write(8'b00000010, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // The THReg is empty
      // Line Status Register
      cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      // Now we cleared the interrupt by reading the IIReg
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // Enable FIFOs - FC register
      cpu_write(8'b00000001, fcradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      // Caused an interrupt by enabling the FIFOs
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // The FIFOs are enabled and the THReg is empty - Line Status Register
      cpu_read(iiradd, 8'b11000010, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      // Now we cleared the interrupt by reading the IIReg
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // Disable FIFOs - FC register
      cpu_write(8'b00000000, fcradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      // Caused an interrupt by enabling the FIFOs
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // The FIFOs are disabled and the THReg is empty
      // Line Status Register
      cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      // Now we cleared the interrupt by reading the IIReg
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // Enable received data interrupt - IE register
      cpu_write(8'b00000001, ieradd, 1'b0); 
      // Re-enable FIFOs - FC register
      cpu_write(8'b00000001, fcradd, 1'b0); 
      // Transmit and receive a character - TH register
      cpu_write(8'b10010110, thradd, 1'b0); 
      // wait for character to be received
      wait_n_cycle(600); 
      @(posedge clk); 
      #cpu_tpd; 
      // Caused an interrupt by receiving a character
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // Clear transmitter FIFO - FC register
      cpu_write(8'b00000101, fcradd, 1'b0); 
      // Clear transmitter FIFO - LC register
      cpu_write(8'b00000101, lcradd, 1'b0); 
      wait_n_cycle(100); 
      $display (" %d ERROR(S)", errors);
      test_done <= 1'b1 ; 
      forever #100000; 
   end

endmodule