h16550tb1.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

      cs <= 1'b0 ; 
      ads <= 1'b0 ; 
      a <= 3'b000 ; 
      @(negedge mr); 
      wait_n_cycle(10); 
      //--------------------------------------------------------------------
      // The first action is to write an initial value to every register
      // outputs DTR, RTS, OUT1 and OUT2 will be checked
      // also values of the registers will be checked
      //--------------------------------------------------------------------
      $display("\n    MPU writes initial registers\n");
      // Line Control register
      cpu_write(initlcr, lcradd, 1'b0); 
      // MODEM Control register
      cpu_write(initmcr, mcradd, 1'b0); 
      $display("\n    Enable Interrupts\n"); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // IE register
      cpu_write(initier, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      $display("\n    Write to SCRATCH register"); 
      cpu_write(initsr, sradd, 1'b0); 
      $display("\n    Write to FIFO CONTROL register"); 
      cpu_write(initfcr0, fcradd, 1'b0); 
      $display("\n    Write to LINE CONTROL register"); 
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n    Write to DIVISOR LSB register"); 
      cpu_write(initdlr, dlradd, 1'b1); 
      $display("\n    Write to DIVISOR MSB register"); 
      cpu_write(initdmr, dmradd, 1'b1); 
      wait_n_cycle(10); 
      $display("\n    MPU Reads initialized registers"); 
      $display("\n    Write to LINE CONTROL register"); 
      cpu_write(initlcr, lcradd, 1'b0); 
      $display("\n    Read LINE CONTROL register"); 
      cpu_read(lcradd, initlcr, 1'b0, 1'b1); 
      $display("\n    Read MODEM CONTROL register"); 
      cpu_read(mcradd, initmcr, 1'b0, 1'b1); 
      $display("\n    Read INTERRUPT ENABLE register"); 
      cpu_read(ieradd, initier, 1'b0, 1'b1); 
      $display("\n    Read SCRATCH register"); 
      cpu_read(sradd, initsr, 1'b0, 1'b1); 
      //---------------------------------------------
      // Registers have been written and read once  --
      //---------------------------------------------
      $display("\n    Write to LINE CONTROL register"); 
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n    Read DIVISOR LSB register"); 
      cpu_read(dlradd, initdlr, 1'b1, 1'b1); 
      $display("\n    Read DIVISOR MSB register"); 
      cpu_read(dmradd, initdmr, 1'b1, 1'b1); 
      $display("\n    Read MODEM STATUS register"); 
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      $display("\n    Read LINE STATUS register"); 
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display("\n    Write LINE CONTROL register"); 
      cpu_write(initlcr, lcradd, 1'b0); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, "UUUUUUUU", 1'b0, 1'b0); 
      $display("\n\n    Read INTERRUPT IDENTIFICATION register"); 
      cpu_read(iiradd, 8'b11000010, 1'b0, 1'b1); 
      $display("\n    Read MODEM STATUS register"); 
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      //-------------------------------------------------------------------------
      // The UART starts to transmit data to itself
      // Number of data and stop bits and parity information is presented to command window
      //-------------------------------------------------------------------------
      $display("\n    TESTING TRANSMISSION AND RECEIVING with few writings to XMIT FIFO and same readings from RCVR FIFO"); 
      $display("    UART transmits data to itself"); 
      $display("\n    Write LINE CONTROL register"); 
      cpu_write(initlcr, lcradd, 1'b0); 
      $display("\n    Check Line status reg, are THRE and TEMP bits active"); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display("\n    Write Transmitter holding register"); 
      cpu_write(initthr0, thradd, 1'b0); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b00000000, 1'b0, 1'b1); 
      begin : xhdl_76
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            // Write Transmitter Holding register
            cpu_write(initthr0, thradd, 1'b0); 
            cpu_write(initthr1, thradd, 1'b0); 
            cpu_write(initthr2, thradd, 1'b0); 
         end
      end 
      // Transmitter Holding register
      cpu_write(initthr2, thradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (txrdyn == 1'b1)
      begin
         $display ($stime,,"ns  TXRDY = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  TXRDY = 0  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(320); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      wait_n_cycle(4540); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b1)
      begin
         // RXRDY hasn\'t activated
         $display ($stime,,"ns  RXRDY = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 0  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(40); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b0)
      begin
         // RXRDY is active
         $display ($stime,,"ns  RXRDY = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // MODE 1 TRIGGER LEVEL 14
      // FIFO Control register ; trigger level 8
      cpu_write(initfcr2, fcradd, 1'b0); 
      wait_n_cycle(1000); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b0)
      begin
         $display ($stime,,"ns  RXRDY = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b00100001, 1'b0, 1'b1); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      begin : xhdl_90
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
            cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
            cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
         end
      end 
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b1)
      begin
         $display ($stime,,"ns  RXRDY = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 0  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(100); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      wait_n_cycle(400); 
      @(posedge clk); 
      #cpu_tpd; 
      if (txrdyn == 1'b0)
      begin
         $display ($stime,,"ns  TXRDY = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  TXRDY = 1  NOK");
         errors <= errors + 1 ; 
      end 
      begin : xhdl_98
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            // Transmitter Holding register
            cpu_write(initthr0, thradd, 1'b0); 
            cpu_write(initthr1, thradd, 1'b0); 
            cpu_write(initthr2, thradd, 1'b0); 
         end
      end 
      cpu_write(initthr0, thradd, 1'b0); 
      cpu_write(initthr1, thradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (txrdyn == 1'b1)
      begin
         $display ($stime,,"ns  TXRDY = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  TXRDY = 0  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(2750); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b1)
      begin
         // RXRDY hasn\'t activated
         $display ($stime,,"ns  RXRDY = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 0  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(40); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b0)
      begin
         // RXRDY is active
         $display ($stime,,"ns  RXRDY = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // FIFO Control register; trigger level 4
      cpu_write(initfcr3, fcradd, 1'b0); 
      //if (txrdyn != 1'b0)
      //begin
      //   @(negedge txrdyn); 
      //end 
      $display("\n    First Wait"); 
      wait_n_cycle(3130); 
      begin : xhdl_110
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            // RECEIVE BUFFER Register
            cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
            cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
            cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
         end
      end 
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      begin : xhdl_111
         integer i;
         for(i = 0; i <= 2; i = i + 1)
         begin
            // Transmitter Holding register
            cpu_write(initthr0, thradd, 1'b0); 
            cpu_write(initthr1, thradd, 1'b0); 
            cpu_write(initthr2, thradd, 1'b0); 
         end
      end 
      wait_n_cycle(1370); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b1)
      begin
         // RXRDY hasn\'t activated
         $display ($stime,,"ns  RXRDY = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 0  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(40); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b0)
      begin
         // RXRDY is active
         $display ($stime,,"ns  RXRDY = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 1  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(100); 
      // FIFO Control register; RESET XMIT FIFO
      cpu_write(initfcr4, fcradd, 1'b0); 
      wait_n_cycle(250); 
      // FIFO Control register; reset RCVR FIFO
      cpu_write(initfcr5, fcradd, 1'b0); 
      wait_n_cycle(100); 
      //--------------------------------------------------------
      // MODE 0 V
      //--------------------------------------------------------
      $display ($stime,,"ns                    MODE 0 test ->");
      wait_n_cycle(100); 
      // FIFO Control register
      cpu_write(initfcr1, fcradd, 1'b0); 
      wait_n_cycle(100); 
      begin : xhdl_121
         integer i;
         for(i = 0; i <= 3; i = i + 1)
         begin
            // Transmitter Holding register
            cpu_write(initthr0, thradd, 1'b0); 
            if (txrdyn == 1'b1)
            begin
               $display ($stime,,"ns  TXRDY = 1 ");
            end
            else if (txrdyn == 1'b0)
            begin
               $display ($stime,,"ns  TXRDY = 0 ");
            end 
            @(negedge txrdyn); 
            $display ($stime,,"ns     Second Wait # %d", i);
            cpu_write(initthr2, thradd, 1'b0); 
            cpu_write(initthr1, thradd, 1'b0); 
         end
      end 
      wait_n_cycle(1250); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      begin : xhdl_125
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            if (rxrdyn == 1'b1) disable xhdl_125; 
            // RECEIVE BUFFER Register
            cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
            if (rxrdyn == 1'b1) disable xhdl_125; 
            cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
            if (rxrdyn == 1'b1) disable xhdl_125; 
            cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
         end
      end 
      if (rxrdyn == 1'b0)
      begin
         $display ($stime,,"ns     Third Wait");
         cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      end 
      if (rxrdyn == 1'b0)
      begin
         $display ($stime,,"ns     Fourth Wait");
         cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      end 
      if (rxrdyn == 1'b0)
      begin
         $display ($stime,,"ns     Fifth Wait");
         cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      end 
      wait_n_cycle(100); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display (" %d ERROR(S)", errors);
      test_done <= 1'b1 ; 
      #period; 
      forever #100000; 
   end
endmodule