h16550tb6.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

                  @(negedge baudout); 
               end
            end 
         end
      end 
      @(posedge enable_sin); 
      index <= 0 ; 
      wait_n_cycle(10); 
      $display($stime,,"ns :   Writing datastream SIN_DATA_OE (11011100)"); 
      begin : xhdl_29
         integer sd4;
         for(sd4 = 0; sd4 <= 7; sd4 = sd4 + 1)
         begin
            sin <= sin_data_oe[index] ; 
            index <= index + 1 ; 
            begin : xhdl_30
               integer bo5;
               for(bo5 = 0; bo5 <= 15; bo5 = bo5 + 1)
               begin
                  @(negedge baudout); 
               end
            end 
         end
      end 
      index <= 0 ; 
      wait_n_cycle(10); 
      $display($stime,,"ns :   Writing datastream SIN_DATA_OE (11011100)"); 
      begin : xhdl_33
         integer sd5;
         for(sd5 = 0; sd5 <= 7; sd5 = sd5 + 1)
         begin
            sin <= sin_data_oe[index] ; 
            index <= index + 1 ; 
            begin : xhdl_34
               integer bo6;
               for(bo6 = 0; bo6 <= 15; bo6 = bo6 + 1)
               begin
                  @(negedge baudout); 
               end
            end 
         end
      end 
      forever #100000; 
   end 

   //-------------------------------------
   // MAIN PROCESS 
   //
   // This process writes and reads registers and checks interrupts
   // Most important attention is paid to interrupt priorities and those enable register 
   //-------------------------------------
   always 
   begin : full_test
      din <= 8'b00000000 ; 
      rd <= 1'b0 ; 
      wr <= 1'b0 ; 
      cs <= 1'b0 ; 
      ads <= 1'b0 ; 
      a <= 3'b000 ; 
      @(negedge mr); 
      wait_n_cycle(10); 
      $display("\n   MPU writes initial registers"); 
      // LINE Control register
      cpu_write(initlcr, lcradd, 1'b0); 
      // MODEM Control register
      cpu_write(initmcr, mcradd, 1'b0); 
      $display("\n   Enable Interrupts"); 
      cpu_write(initier, ieradd, 1'b0); 
      $display("\n   Write to LINE CONTROL register"); 
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n   Write to DIVISOR LSB register"); 
      cpu_write(initdlr, dlradd, 1'b1); 
      $display("\n   Write to DIVISOR MSB register"); 
      cpu_write(initdmr, dmradd, 1'b1); 
      wait_n_cycle(10); 
      $display("\n   MPU READs initialized registers"); 
      $display("\n   Write to LINE CONTROL register"); 
      cpu_write(initlcr, lcradd, 1'b0); 
      $display("\n   Read LINE CONTROL register"); 
      cpu_read(lcradd, initlcr, 1'b0, 1'b1); 
      $display("\n   Read MODEM CONTROL register"); 
      cpu_read(mcradd, initmcr, 1'b0, 1'b1); 
      $display("\n   Read INTERRUPT ENABLE register"); 
      cpu_read(ieradd, initier, 1'b0, 1'b1); 
      $display("\n   Write to LINE CONTROL register"); 
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n   READ DIVISOR LSB register"); 
      cpu_read(dlradd, initdlr, 1'b1, 1'b1); 
      $display("\n   READ DIVISOR MSB register"); 
      cpu_read(dmradd, initdmr, 1'b1, 1'b1); 
      $display("\n   Read MODEM STATUS register"); 
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      $display("\n   Read LINE STATUS register"); 
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display("\n   Write LINE CONTROL register"); 
      cpu_write(initlcr, lcradd, 1'b0); 
      $display("\n   TESTING INTERRUPT IDENTIFICATION, ENABLE and LINE STATUS REGISTERS "); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display($stime,,"ns   INTR = 0 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 1 NOK "); 
         errors <= errors + 1 ; 
      end 
      // ENABLE THR empty - IE register
      cpu_write(8'b00001111, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = 3. priority - Interrupt identification Register
      cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); 
      // DISABLE THR empty - IE register
      cpu_write(initier, ieradd, 1'b0); 
      $display("\n   Read INTERRUPT IDENTIFICATION register"); 
      cpu_read(iiradd, 8'b00000001, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display($stime,,"ns   INTR = 0 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 1 NOK "); 
         errors <= errors + 1 ; 
      end 
      $display("\n   Read MODEM STATUS register"); 
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      //-------------------------------------------------------------------------
      // Testbench generates Serial data and checks interrupts 
      //-------------------------------------------------------------------------
      enable_sin <= 1'b1 ; 
      $display("\n   Waiting for Received data available interrupt = 2. PRIORITY"); 
      $display("\n   Other interrupts are disabled"); 
      @(posedge intr); 
      enable_sin <= 1'b0 ; 
      // = 2. priority - Interrupt identification Register
      cpu_read(iiradd, 8'b00000100, 1'b0, 1'b1); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, 8'b00000101, 1'b0, 1'b1); 
      $display("\n   ENABLE Receiver line status interrupt = 1. PRIORITY"); 
      // = Enable Reveiver line status interrupt - IE register
      cpu_write(8'b00000100, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = 1. priority - Interrupt identification Register
      cpu_read(iiradd, 8'b00000110, 1'b0, 1'b1); 
      $display("\n   ENABLE Transmitter holding register interrupt"); 
      // = Enable all interrupts except THReg empty -- IE register
      cpu_write(8'b00001101, ieradd, 1'b0); 
      $display("\n   Read PARITY ERROR from LINE STATUS register"); 
      // PARITY ERROR -- LINE STATUS Register
      cpu_read(lsradd, 8'b01100100, 1'b0, 1'b1); 
      // = no interrupts -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000001, 1'b0, 1'b1); 
      // = Enable all interrupts -- IE register
      cpu_write(8'b00001101, ieradd, 1'b0); 
      enable_sin <= 1'b1 ; 
      @(posedge intr); 
      cts <= 1'b0 ; 
      enable_sin <= 1'b0 ; 
      // = Disable all interrupts -- IE register
      cpu_write(8'b00000000, ieradd, 1'b0); 
      // = no interrupts -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000001, 1'b0, 1'b1); 
      // = Enable all interrupts -- IE register
      cpu_write(8'b00001111, ieradd, 1'b0); 
      // = 1. Priority -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000110, 1'b0, 1'b1); 
      // = Disable RL Status -- IE register
      cpu_write(8'b00001011, ieradd, 1'b0); 
      // = 2. Priority -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000100, 1'b0, 1'b1); 
      // = Disable RD available -- IE register
      cpu_write(8'b00001010, ieradd, 1'b0); 
      // = 4. PRIORITY -- Interrupt identification Register
      //cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); 
      cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); 
      // = Enable all interrupts -- IE register
      cpu_write(8'b00001111, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // RECEIVER DATA READY, FRAME ERROR -- LINE STATUS Register
      cpu_read(lsradd, 8'b01101001, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = 2. Priority -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000100, 1'b0, 1'b1); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, 8'b00000111, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = 4. PRIORITY -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); 
      // MODEM STATUS Register
      cpu_read(msradd, 8'b00010001, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display($stime,,"ns   INTR = 0 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 1 NOK "); 
         errors <= errors + 1 ; 
      end 
      enable_sin <= 1'b1 ; 
      //@(posedge intr); 
      @(posedge sin);
      // = Disable RL Status -- IE register
      cpu_write(8'b00001011, ieradd, 1'b0); 
      wait_n_cycle(6);

      //if (intr == 1'b0)
      //begin
      //   // in case intr is not 1 yet, wait for it
      //   @(posedge intr); 
      //end // otherwise go on with life 

      // = 2. Priority -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000100, 1'b0, 1'b1); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, 8'b00000000, 1'b0, 1'b1); 
      // = Disable Received data available interrupt -- IE register
      cpu_write(8'b00001110, ieradd, 1'b0); 
      //  FRAME ERROR , BREAK INTERRUPT -- LINE STATUS Register
      cpu_read(lsradd, 8'b01111000, 1'b0, 1'b1); 
      enable_sin <= 1'b0 ; 
      //@(posedge intr); 
      wait_n_cycle(150);
      //  RECEIVER DATA READY, PARITY ERROR -- LINE STATUS Register
      cpu_read(lsradd, 8'b01100101, 1'b0, 1'b1); 
      //  RECEIVER DATA READY -- LINE STATUS Register
      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); 
      // = Enable all interrupts -- IE register
      cpu_write(8'b00001111, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, 8'b00011100, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      //-----------------------------
      // Operate all interrupts ON
      //----------------------------- 
      wait_n_cycle(30); 
      enable_sin <= 1'b1 ; 
      // = Enable all interrupts -- IE register
      cpu_write(8'b00001111, ieradd, 1'b0); 
      // write THR
      cpu_write(initthr, thradd, 1'b0); 
      dcd <= 1'b0 ; 
      @(negedge sin);   // JS
      //wait_n_cycle(150);   // JS
      wait_n_cycle(143);   // JS
      enable_sin <= 1'b0 ; 
      // = Disable all interrupts -- IE register
      cpu_write(8'b00000000, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display($stime,,"ns   INTR = 0 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 1 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Enable Receiver data availabe -- IE register
      cpu_write(8'b00000001, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Disable all interrupts -- IE register
      cpu_write(8'b00000000, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display($stime,,"ns   INTR = 0 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 1 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Enable Transmitter holding register interrupt -- IE register
      cpu_write(8'b00000010, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Disable all interrupts -- IE register
      cpu_write(8'b00000000, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display($stime,,"ns   INTR = 0 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 1 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Enable Receiver line status -- IE register
      cpu_write(8'b00000100, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Disable all interrupts -- IE register
      cpu_write(8'b00000000, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display($stime,,"ns   INTR = 0 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 1 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Enable MODEM status interrupts -- IE register
      cpu_write(8'b00001000, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display($stime,,"ns   INTR = 1 OK "); 
      end
      else
      begin
         $display($stime,,"ns   INTR = 0 NOK "); 
         errors <= errors + 1 ; 
      end 
      // = Enable THR int.  -- IE register
      cpu_write(8'b00000010, ieradd, 1'b0); 
      // = 3. Priority -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); 
      // = Enable THR and MODEM status int.  -- IE register
      cpu_write(8'b00001010, ieradd, 1'b0); 
      // = 4. Priority -- Interrupt identification Register
      //cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); 
      cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); 
      // = Enable THR, MS and Receiver data available -- IE register
      cpu_write(8'b00001011, ieradd, 1'b0); 
      // = 2. Priority -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000100, 1'b0, 1'b1); 
      // = Enable all interrupts -- IE register
      cpu_write(8'b00001111, ieradd, 1'b0); 
      // = 2. Priority -- Interrupt identification Register
      cpu_read(iiradd, 8'b00000110, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100101, 1'b0, 1'b1); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, 8'b00000011, 1'b0, 1'b1); 
      // Modem status Register
      cpu_read(msradd, 8'b10011000, 1'b0, 1'b1); 
      enable_sin <= 1'b1 ; 
      @(posedge intr); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); 
      @(negedge sin);   // JS
      //wait_n_cycle(150);  // JS
      wait_n_cycle(138);  // JS
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100011, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); 
      $display (" %d ERROR(S)", errors);
      done <= 1'b1 ; 
      forever #100000; 
   end

endmodule