h16550tb5.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

   always 
   begin : full_test
      din <= 8'b00000000 ; 
      rd <= 1'b0 ; 
      wr <= 1'b0 ; 
      cs <= 1'b0 ; 
      ads <= 1'b0 ; 
      a <= 3'b000 ; 
      @(posedge clk); 
      #cpu_tpd; 
      if (dtr == 1'b1)
      begin
         $display("\n   DTR output during RESET  OK"); 
      end
      else
      begin
         $display("\n   DTR output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      if (rts == 1'b1)
      begin
         $display("   RTS output during RESET  OK"); 
      end
      else
      begin
         $display("   RTS output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      if (out1 == 1'b1)
      begin
         $display("   OUT1 output during RESET  OK"); 
      end
      else
      begin
         $display("   OUT1 output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      if (out2 == 1'b1)
      begin
         $display("   OUT2 output during RESET  OK"); 
      end
      else
      begin
         $display("   OUT2 output during RESET  NOK"); 
         errors <= errors + 1 ; 
      end 
      @(negedge mr); 
      wait_n_cycle(10); 
      //--------------------------------------------------------------------
      // The first action is to write an initial value to every register
      // outputs DTR, RTS, OUT1 and OUT2 will be checked
      // also values of the registers will be checked
      //--------------------------------------------------------------------
      $display("\n   MPU writes initial registers"); 
      // LINE Control register
      cpu_write(initlcr, lcradd, 1'b0); 
      // MODEM Control register
      cpu_write(initmcr, mcradd, 1'b0); 
      $display("\n   Check outputs: DTR, RTS, OUT1 and OUT2 "); 
      if ((initmcr[4]) == 1'b1)
      begin
         // LOOP
         $display("\n     LOOP MODE!"); 
         @(posedge clk); 
         #cpu_tpd; 
         if (dtr == 1'b1)
         begin
            $display($stime,,"ns  DTR output OK"); 
         end
         else
         begin
            $display($stime,,"ns  DTR output NOK"); 
            errors <= errors + 1 ; 
         end 
         if (rts == 1'b1)
         begin
            $display($stime,,"ns  RTS output OK"); 
         end
         else
         begin
            $display($stime,,"ns  RTS output NOK"); 
            errors <= errors + 1 ; 
         end 
         if (out1 == 1'b1)
         begin
            $display($stime,,"ns  OUT1 output OK"); 
         end
         else
         begin
            $display($stime,,"ns  OUT1 output NOK"); 
            errors <= errors + 1 ; 
         end 
         if (out2 == 1'b1)
         begin
            $display($stime,,"ns  OUT2 output OK"); 
         end
         else
         begin
            $display($stime,,"ns  OUT2 output NOK"); 
            errors <= errors + 1 ; 
         end 
      end
      else
      begin
         @(posedge clk); 
         #cpu_tpd; 
         if (dtr != initmcr[0])
         begin
            $display($stime,,"ns  DTR output OK"); 
         end
         else
         begin
            $display($stime,,"ns  DTR output NOK"); 
            errors <= errors + 1 ; 
         end 
         if (rts != initmcr[1])
         begin
            $display($stime,,"ns  RTS output OK"); 
         end
         else
         begin
            $display($stime,,"ns  RTS output NOK"); 
            errors <= errors + 1 ; 
         end 
         if (out1 != initmcr[2])
         begin
            $display($stime,,"ns  OUT1 output OK"); 
         end
         else
         begin
            $display($stime,,"ns  OUT1 output NOK"); 
            errors <= errors + 1 ; 
         end 
         if (out2 != initmcr[3])
         begin
            $display($stime,,"ns  OUT2 output OK"); 
         end
         else
         begin
            $display($stime,,"ns  OUT2 output NOK"); 
            errors <= errors + 1 ; 
         end 
      end 
      $display("\n   Enable Interrupts"); 
      cpu_write(initier, ieradd, 1'b0); 
      $display("\n   Write to SCRATCH register"); 
      cpu_write(initsr, sradd, 1'b0); 
      $display("\n   Write to LINE CONTROL register"); 
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n   Write to DIVISOR LSB register"); 
      cpu_write(initdlr, dlradd, 1'b1); 
      $display("\n   Write to DIVISOR MSB register"); 
      cpu_write(initdmr, dmradd, 1'b1); 
      wait_n_cycle(10); 
      $display("\n   MPU READs initialized registers"); 
      $display("\n   Write to LINE CONTROL register"); 
      cpu_write(initlcr, lcradd, 1'b0); 
      $display("\n   Read LINE CONTROL register"); 
      cpu_read(lcradd, initlcr, 1'b0, 1'b1); 
      $display("\n   Read MODEM CONTROL register"); 
      cpu_read(mcradd, initmcr, 1'b0, 1'b1); 
      $display("\n   Read INTERRUPT ENABLE register"); 
      cpu_read(ieradd, initier, 1'b0, 1'b1); 
      $display("\n   Read SCRATCH register"); 
      cpu_read(sradd, initsr, 1'b0, 1'b1); 
      $display("\n   Write to LINE CONTROL register"); 
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n   READ DIVISOR LSB register"); 
      cpu_read(dlradd, initdlr, 1'b1, 1'b1); 
      $display("\n   READ DIVISOR MSB register"); 
      cpu_read(dmradd, initdmr, 1'b1, 1'b1); 
      $display("\n   Read MODEM STATUS register"); 
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      $display("\n   Read LINE STATUS register"); 
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display("\n   Write LINE CONTROL register"); 
      cpu_write(initlcr, lcradd, 1'b0); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, "UUUUUUUU", 1'b0, 1'b0); 
      $display("\n   Read INTERRUPT IDENTIFICATION register"); 
      cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); 
      $display("\n   Read MODEM STATUS register"); 
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      //-------------------------------------------------------------------------
      // The UART starts to transmit data to itself
      // Number of data and stop bits and parity information is presented to command window
      //-------------------------------------------------------------------------
      $display("\n   TESTING TRANSMISSION AND RECEIVING with 16 different frames"); 
      begin : xhdl_91
         integer tcase;
         for(tcase = 1; tcase <= 7; tcase = tcase + 1)
         begin
            $display("\n  UART transmits data to itself"); 
            $display("\n   CASE =  %d", tcase);
            cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
            $display("\n  Write to DIVISOR LSB register"); 
            cpu_write(initdlr, dlradd, 1'b1); 
            $display("\n  Write to DIVISOR MSB register"); 
            cpu_write(initdmr, dmradd, 1'b1); 
            testcase <= testcase + 1 ; 
            $display("\n  Write LINE CONTROL register"); 
            cpu_write(initlcr, lcradd, 1'b0); 
            $display("\n  Write Transmitter holding register"); 
            cpu_write(initthr, thradd, 1'b0); 
            data <= 8'b00000000 ; 
            begin : xhdl_101
               integer i;
               for(i = 0; i <= 3; i = i + 1)
               begin
                  @(negedge baudout); 
               end
            end 
            if (initlcr[1:0] == 2'b00)
            begin
               $display("\n  5 data bits "); 
            end
            else if (initlcr[1:0] == 2'b01)
            begin
               $display("\n  6 data bits "); 
            end
            else if (initlcr[1:0] == 2'b10)
            begin
               $display("\n  7 data bits "); 
            end
            else
            begin
               $display("\n  8 data bits "); 
            end 
            if ((initlcr[2]) == 1'b0)
            begin
               $display("  1 STOP bit "); 
            end
            else if ((initlcr[2]) == 1'b1 & initlcr[1:0] == 2'b00)
            begin
               $display("  1.5 STOP bits "); 
            end
            else
            begin
               $display("  2 STOP bits "); 
            end 
            if ((initlcr[3]) == 1'b0)
            begin
               $display("  PARITY disabled "); 
            end
            else
            begin
               $display("  PARITY enabled"); 
               if ((initlcr[5]) == 1'b0)
               begin
                  $display("\n  STICK parity disabled"); 
                  if ((initlcr[4]) == 1'b0)
                  begin
                     $display("  ODD parity "); 
                  end
                  else
                  begin
                     $display("  EVEN parity "); 
                  end 
               end
               else
               begin
                  $display("  STICK parity enabled"); 
                  if ((initlcr[4]) == 1'b0)
                  begin
                     $display("  STICK parity bit is checked as '1'"); 
                  end
                  else
                  begin
                     $display("  STICK parity bit is checked as '0'"); 
                  end 
               end 
            end 
            begin : xhdl_117
               integer i;
               for(i = 0; i <= 145; i = i + 1)
               begin
                  @(negedge baudout); 
               end
            end 
            //-------------------------------------------------------------------------------------
            // The next loop is done for polling THRE bit in Line status register 
            // When it is \'1\' the Transmitter holding register is empty and next message data could be written
            //-------------------------------------------------------------------------------------
            data <= 8'b00000000 ; 
            begin : xhdl_118
               forever
               begin
                  if ((data[5]) == 1'b1) disable xhdl_118; 
                  // LINE STATUS Register
                  // The result is not checked because each Tcase will have
                  // different result
                  cpu_read(lsradd, 8'b00000000, 1'b0, 1'b0); 
                  data <= dout ; 
                  wait_n_cycle(100); 
               end
            end 
            //-------------------------------------------------------------------------------------
            // The next loop is done for polling DR bit in Line status register 
            // When it is \'1\' the Receive buffer register contains message data and it can be read
            //-------------------------------------------------------------------------------------
            data <= 8'b00000000 ; 
            begin : xhdl_119
               forever
               begin
                  if ((data[0]) == 1'b1) disable xhdl_119; 
                  // LINE STATUS Register
                  // The result is not checked because each Tcase will have
                  // different result
                  cpu_read(lsradd, 8'b00000000, 1'b0, 1'b0); 
                  data <= dout ; 
                  wait_n_cycle(100); 
               end
            end 
            wait_n_cycle(10); 
            // Interrupt identification Register
            cpu_read(iiradd, 8'b00000100, 1'b0, 1'b1); 
            // RECEIVE BUFFER Register
            cpu_read(rbradd, ({(initthr[7] & initlcr[1] & initlcr[0]), (initthr[6] &
            initlcr[1]), (initthr[5] & (initlcr[1] | initlcr[0])), initthr[4:0]}), 1'b0, 1'b1); 
            if (tcase == 1)
            begin
               initlcr <= 8'b00101110 ; // CASE 2
               initdlr <= 8'b00000001 ; 
               initdmr <= 8'b00000000 ; 
            end
            else if (tcase == 2)
            begin
               initlcr <= 8'b00111010 ; 
               initdlr <= 8'b00000010 ; 
               initdmr <= 8'b00000000 ; 
            end
            else if (tcase == 3)
            begin
               initlcr <= 8'b00011110 ; 
               initdlr <= 8'b00000011 ; 
               initdmr <= 8'b00000000 ; 
            end
            else if (tcase == 4)
            begin
               initlcr <= 8'b00010100 ; 
               initdlr <= 8'b11111111 ; 
               initdmr <= 8'b00000000 ; 
            end
            else if (tcase == 5)
            begin
               initlcr <= 8'b00101000 ; 
               initdlr <= 8'b00000000 ; 
               initdmr <= 8'b00000001 ; 
            end
            else if (tcase == 6)
            begin
               initlcr <= 8'b00111000 ; 
               initdlr <= 8'b00000001 ; 
               initdmr <= 8'b00000001 ; 
            end
            else if (tcase == 7)
            begin
               initlcr <= 8'b00111010 ; 
               initdlr <= 8'b00000001 ; 
               initdmr <= 8'b00000000 ; 
            end 
            initthr <= ~initlcr ; // Different message data
            begin : xhdl_120
               integer i;
               for(i = 0; i <= 15; i = i + 1)
               begin
                  @(negedge baudout); 
               end
            end 
         end
      end // ALL 16 CASES
      $display (" %d ERROR(S)", errors);
      test_done <= 1'b1 ; 
      forever #100000; 
   end

endmodule