h16550tb2.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

      cpu_read(lsradd, 8'b00000101, 1'b0, 1'b1); 
      // 8. sample + error
      // Error shifted when clock changed - RECEIVE BUFFER Register
      //cpu_read(rbradd, 8'b01110100, 1'b0, 1'b1); 
      cpu_read(rbradd, 8'b00010100, 1'b0, 1'b1); 
      // DR, LSR7   -- When LSR is read, bit 7 is cleared - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 9. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      // DR, LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 10. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00001001, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // 11. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 12. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 13. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 14. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000101, 1'b0, 1'b1); 
      // 15. sample + error - RECEIVE BUFFER Register
      cpu_read(rbradd, (initthr1 & 8'b11111011), 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000000, 1'b0, 1'b1); 
      wait_n_cycle(500); 
      // Transmitter Holding register
      cpu_write(initthr0, thradd, 1'b0); 
      cpu_write(initthr1, thradd, 1'b0); 
      cpu_write(initthr0, thradd, 1'b0); 
      cpu_write(initthr1, thradd, 1'b0); 
      wait_n_cycle(1400); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b10000001, 1'b0, 1'b1); 
      // 16. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 17. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000101, 1'b0, 1'b1); 
      // 18. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, (initthr0 & 8'b10111111), 1'b0, 1'b1); 
      // DR, FE , LSR7 - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 19. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      // DR, FE , LSR7  -- should be cleared - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 20. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      wait_n_cycle(1000); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // disables transmitter holding register empty int - IE register
      cpu_write((initier & 8'b11111101), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // enables all interrupts - IE register
      cpu_write(initier, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // 21. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); 
      // 22. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); 
      // 23. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      wait_n_cycle(100); 
      // LINE Control register
      cpu_write(8'b00001000, lcradd, 1'b0); 
      begin : xhdl_131
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            // Transmitter Holding register
            cpu_write(initthr0, thradd, 1'b0); 
            cpu_write(initthr1, thradd, 1'b0); 
            cpu_write(initthr2, thradd, 1'b0); 
         end
      end 
      cpu_write(initthr0, thradd, 1'b0); 
      cpu_write(initthr1, thradd, 1'b0); 
      wait_n_cycle(2000); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      wait_n_cycle(2400); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // enables transmitter holding register empty int - IE register
      cpu_write((initier & 8'b11110010), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // THR empty - Interrupt identification Register
      cpu_read(iiradd, 8'b11000010, 1'b0, 1'b1); 
      // Interrupt identification Register
      cpu_read(iiradd, 8'b11000001, 1'b0, 1'b1); 
      // disables all interrupts - IE register
      cpu_write((initier & 8'b11110000), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // Interrupt identification Register
      cpu_read(iiradd, 8'b11000001, 1'b0, 1'b1); 
      // enables receiver line status int - IE register
      cpu_write((initier & 8'b11110100), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // Interrupt identification Register
      cpu_read(iiradd, 8'b11000110, 1'b0, 1'b1); 
      // disables all interrupts - IE register
      cpu_write((initier & 8'b11110000), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // Interrupt identification Register
      cpu_read(iiradd, 8'b11000001, 1'b0, 1'b1); 
      // enables received data avail int - IE register
      cpu_write((initier & 8'b11110001), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // RDA int - Interrupt identification Register
      cpu_read(iiradd, 8'b11000100, 1'b0, 1'b1); 
      // disables all interrupts - IE register
      cpu_write((initier & 8'b11110000), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // enables all interrupts - IE register
      cpu_write(initier, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      wait_n_cycle(200); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100011, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); 
      // Resets RCVR FIFO - FIFO Control register
      cpu_write(initfcr1, fcradd, 1'b0); 
      wait_n_cycle(10); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      wait_n_cycle(10); 
      begin : xhdl_156
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            // Transmitter Holding register
            cpu_write(initthr0, thradd, 1'b0); 
            cpu_write(initthr1, thradd, 1'b0); 
            cpu_write(initthr2, thradd, 1'b0); 
         end
      end 
      cpu_write(initthr0, thradd, 1'b0); 
      cpu_write(initthr1, thradd, 1'b0); 
      wait_n_cycle(2000); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      wait_n_cycle(2600); 
      // Overrun error = \'1\' - LINE STATUS Register
      cpu_read(lsradd, 8'b01100011, 1'b0, 1'b1); 
      // Overrun error = \'0\' - LINE STATUS Register
      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); 
      // RDA int - Interrupt identification Register
      cpu_read(iiradd, 8'b11000100, 1'b0, 1'b1); 
      // 5 bits - RECEIVE BUFFER Register
      cpu_read(rbradd, (initthr0 & 8'b00011111), 1'b0, 1'b1); 
      // 5 bits - RECEIVE BUFFER Register
      cpu_read(rbradd, (initthr1 & 8'b00011111), 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // FIFO drops below the trigger level after next reading
      // Interrupt will be reset
      // 5 bits - RECEIVE BUFFER Register
      cpu_read(rbradd, (initthr2 & 8'b00011111), 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      begin : xhdl_163
         integer i;
         for(i = 0; i <= 3; i = i + 1)
         begin
            // 5 bits - RECEIVE BUFFER Register
            cpu_read(rbradd, (initthr0 & 8'b00011111), 1'b0, 1'b1); 
            cpu_read(rbradd, (initthr1 & 8'b00011111), 1'b0, 1'b1); 
            cpu_read(rbradd, (initthr2 & 8'b00011111), 1'b0, 1'b1); 
         end
      end 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, (initthr0 & 8'b00011111), 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display (" %d ERROR(S)", errors);
      test_done <= 1'b1 ; 
      forever #100000; 
   end

endmodule