h16550tb2.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

   // Infinite clock generator
   //-------------------------------------------------
   always @(baudout)
   begin
      if ($time > 9990)
      begin
         rclk <= ~(baudout) ; 
      end 
   end 

   //-------------------------------------------------
   // Asynchronous reset
   //-------------------------------------------------
   always 
   begin
      #50; 
      mr <= 1'b1 ; 
      #230; 
      mr <= 1'b0 ; 
      begin : xhdl_4
         integer i;
         for(i = 248; i >= 0; i = i - 1)
         begin
            @(posedge clk); 
         end
      end 
      begin : xhdl_6
         integer i;
         for(i = 0; i <= 5; i = i + 1)
         begin
            begin : xhdl_7
               integer i;
               for(i = 149; i >= 0; i = i - 1)
               begin
                  @(posedge clk); 
               end
            end 
            @(posedge rclk); 
            set_error <= 1'b1 ; 
            begin : xhdl_9
               integer i;
               for(i = 0; i <= 15; i = i + 1)
               begin
                  @(posedge rclk); 
               end
            end 
            set_error <= 1'b0 ; 
            begin : xhdl_10
               integer i;
               for(i = 999; i >= 0; i = i - 1)
               begin
                  @(posedge clk); 
               end
            end 
         end
      end 
      forever #100000; 
   end 

   always 
   begin : xhdl_16
      forever
      begin
         #(period / 2); 
         clk <= ~clk ; 
         if (test_done)
         begin
            clk <= ~clk ;
            $display("TEST COMPLETE");
            if (errors == 0)
            begin
               $display("There were no errors");
            end
            else
            begin
               $display("There were %d Errors", errors);
            end
            forever #100000;
         end 
      end 
   end 

   always @(sout or set_error)
   begin
      if (set_error == 1'b0)
      begin
         sin <= sout ; 
      end
      else
      begin
         sin <= ~sout ; 
      end 
   end 

   always 
   begin : full_test
      din <= 8'b00000000 ; 
      rd <= 1'b0 ; 
      wr <= 1'b0 ; 
      cs <= 1'b0 ; 
      ads <= 1'b0 ; 
      a <= 3'b000 ; 
      @(negedge mr); 
      wait_n_cycle(10); 
      //--------------------------------------------------------------------
      // The first action is to write an initial value to every register
      // outputs DTR, RTS, OUT1 and OUT2 will be checked
      // also values of the registers will be checked
      //--------------------------------------------------------------------
      $display("\n    MPU writes initial registers\n");
      // LINE Control register
      cpu_write(initlcr, lcradd, 1'b0); 
      // MODEM Control register
      cpu_write(initmcr, mcradd, 1'b0); 
      $display("\n    Enable Interrupts\n");
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // IE register
      cpu_write(initier, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      $display("\n    Write to SCRATCH register");
      cpu_write(initsr, sradd, 1'b0); 
      $display("\n    Write to FIFO CONTROL register");
      cpu_write(initfcr0, fcradd, 1'b0); 
      $display("\n    Write to LINE CONTROL register");
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n    Write to DIVISOR LSB register");
      cpu_write(initdlr, dlradd, 1'b1); 
      $display("\n    Write to DIVISOR MSB register");
      cpu_write(initdmr, dmradd, 1'b1); 
      wait_n_cycle(10); 
      $display("\n    MPU Reads initialized registers");
      $display("\n    Write to LINE CONTROL register");
      cpu_write(initlcr, lcradd, 1'b0); 
      $display("\n    Read LINE CONTROL register");
      cpu_read(lcradd, initlcr, 1'b0, 1'b1); 
      $display("\n    Read MODEM CONTROL register");
      cpu_read(mcradd, initmcr, 1'b0, 1'b1); 
      $display("\n    Read INTERRUPT ENABLE register");
      cpu_read(ieradd, initier, 1'b0, 1'b1); 
      $display("\n    Read SCRATCH register");
      cpu_read(sradd, initsr, 1'b0, 1'b1); 
      //---------------------------------------------
      // Registers have been written and read once  --
      //---------------------------------------------
      $display("\n    Write to LINE CONTROL register");
      cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); 
      $display("\n    Read DIVISOR LSB register");
      cpu_read(dlradd, initdlr, 1'b1, 1'b1); 
      $display("\n    Read DIVISOR MSB register");
      cpu_read(dmradd, initdmr, 1'b1, 1'b1); 
      $display("\n    Read MODEM STATUS register");
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      $display("\n    Read LINE STATUS register");
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display("\n    Write LINE CONTROL register");
      cpu_write(initlcr, lcradd, 1'b0); 
      // RECEIVE BUFFER Register
      cpu_read(rbradd, "UUUUUUUU", 1'b0, 1'b0); 
      $display("\n\n    Read INTERRUPT IDENTIFICATION register");
      cpu_read(iiradd, 8'b11000010, 1'b0, 1'b1); 
      $display("\n    Read MODEM STATUS register");
      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); 
      //-------------------------------------------------------------------------
      // The UART starts to transmit data to itself
      // Number of data and stop bits and parity information is presented to command window
      //-------------------------------------------------------------------------
      $display("\n    TESTING TRANSMISSION AND RECEIVING with few writings to XMIT FIFO and same readings from RCVR FIFO");
      $display("    UART transmits data to itself");
      $display("\n    Write LINE CONTROL register");
      cpu_write(initlcr, lcradd, 1'b0); 
      $display("\n    Check Line status reg, are THRE and TEMP bits active");
      // LINE STATUS Register
      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); 
      $display("\n    Write Transmitter holding register");
      cpu_write(initthr0, thradd, 1'b0); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b00000000, 1'b0, 1'b1); 
      begin : xhdl_87
         integer i;
         for(i = 0; i <= 4; i = i + 1)
         begin
            // Transmitter Holding register
            cpu_write(initthr0, thradd, 1'b0); 
            cpu_write(initthr1, thradd, 1'b0); 
            cpu_write(initthr2, thradd, 1'b0); 
         end
      end 
      cpu_write(initthr2, thradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (txrdyn == 1'b1)
      begin
         $display ($stime,,"ns  TXRDY = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  TXRDY = 0  NOK");
         errors <= errors + 1 ; 
      end 
      @(posedge intr); 
      // IE register; disables line status interrupt
      cpu_write((initier & 8'b11111011), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // IE register; enables all interrupts
      cpu_write(initier, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // Reciever line status interrupt;  Interrupt identification Register
      cpu_read(iiradd, 8'b11000110, 1'b0, 1'b1); 
      // LINE STATUS Register
      cpu_read(lsradd, 8'b10001001, 1'b0, 1'b1); 
      @(negedge rxrdyn); // mode 1
      wait_n_cycle(500); 
      @(posedge clk); 
      #cpu_tpd; 
      if (rxrdyn == 1'b0)
      begin
         $display ($stime,,"ns  RXRDY = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  RXRDY = 1  NOK");
         errors <= errors + 1 ; 
      end 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // disables received data available int;  IE register
      cpu_write((initier & 8'b11111110), ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // enables all interrupts;  IE register
      cpu_write(initier, ieradd, 1'b0); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // Transmitter Holding register
      cpu_write(initthr0, thradd, 1'b0); 
      cpu_write(initthr1, thradd, 1'b0); 
      // DR & LSR7;  LINE STATUS Register
      cpu_read(lsradd, 8'b10000001, 1'b0, 1'b1); 
      // 1. sample ; RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      // DR, LSR7   -- When LSR is read, bit 7 is cleared;  LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 2. sample;  RECEIVE BUFFER Register
      cpu_read(rbradd, initthr0, 1'b0, 1'b1); 
      // DR, LSR7  When LSR is read, bit 7 is cleared -LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 3. sample ; RECEIVE BUFFER Register
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      // DR, LSR7   When LSR is read, bit 7 is cleared -LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 4. sample;  RECEIVE BUFFER Register
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b1)
      begin
         $display ($stime,,"ns  INTR = 1  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 0  NOK");
         errors <= errors + 1 ; 
      end 
      // DR, LSR7  When LSR is read, bit 7 is cleared - LINE STATUS Register
      cpu_read(lsradd, 8'b00000101, 1'b0, 1'b1); 
      // 5. sample + error
      // Error shifted due to clock change JH - RECEIVE BUFFER Register
      cpu_read(rbradd, 8'b01010000, 1'b0, 1'b1); 
      @(posedge clk); 
      #cpu_tpd; 
      if (intr == 1'b0)
      begin
         $display ($stime,,"ns  INTR = 0  OK");
      end
      else
      begin
         $display ($stime,,"ns  INTR = 1  NOK");
         errors <= errors + 1 ; 
      end 
      // DR, LSR7   -- When LSR is read, bit 7 is cleared - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 6. sample- RECEIVE BUFFER Register
      cpu_read(rbradd, initthr1, 1'b0, 1'b1); 
      // DR, LSR7   -- When LSR is read, bit 7 is cleared - LINE STATUS Register
      cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); 
      // 7. sample - RECEIVE BUFFER Register
      cpu_read(rbradd, initthr2, 1'b0, 1'b1); 
      // DR, LSR7   -- When LSR is read, bit 7 is cleared - LINE STATUS Register