readme.txt

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

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-- Copyright (c) 2002-2003 CAST, Inc.
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-- Please review the terms of the license agreement before using this file.
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H16550 Core


Version History
---------------

  February 2002  : Release 1.1V
  April 2002     : Release 1.2V
                   Size reduced
                   Transmit/Receiver Fifo reset will reset the read/write pointer to 0
  January 2003   : Release 1.3V
                   THRE interrupt problem fixed
  February 2003  : Release 1.4V
                   RXRDY with no data received problem fixed 
  June 2003      : Release 2.0V
                   THRE interrupt problem and delay fixed
                   Break detection problem fixed
                   Rename some of the files to uart_reg, uart_fifo, and rwcontrol
                   Rename RXRDY and TXRDY to RXRDYN and TXRDYN


Description  
-------------
   16550 Universal Asynchronous Receiver/Transmitter with FIFOs


Supplied Files 
--------------

  readme.txt                This file

  doc/
     h16550.pdf             Users Documentation in PDF format

   scripts/ 
     compile.mti            Sample Compile script for ModelSim Simulator
     exemplar.tcl           Sample Exemplar script for Actel, Altera and Xilinx device
     exemplar_altera.tcl    Sample Exemplar script for Altera
     exemplar_xilinx.tcl    Sample Exemplar script for Xilinx
     filelist.txt           Compiling order for Exemplar script
     synopsys.scr           Sample Synopsys synthesis script

  src/
     h16550_params.v        Support file for H16550 model
     h16550w.v              Example of the wrapper to use in a design that requires
                            adsn functionality
     h16550tsw.v            Example of the wrapper to use in a design that requires
                            bi-directional I/O bus
     h16550.v               Top Level entity/architecture
     baudgen.v              Baud Rate Generator
     uart_fifo.v            FIFO model built with registers or RAM
     fifo_altera.v          FIFO model using internal RAM as FIFO (Altera version)
     fifoctrl.v             FIFO controller
     intcontrol.v           Interrupt controller
     rwcontrol.v            Top level signal controller
     uart_reg.v             Programmable registers for entire model
     rxblock.v              Receiver block
     txblock.v              Transmitter block

  tb/
     h16550tb1.v            Testbench1 with auto compare
     h16550tb2.v            Testbench2 with auto compare
     h16550tb3.v            Testbench3 with auto compare
     h16550tb4.v            Testbench4 with auto compare
     h16550tb5.v            Testbench5 with auto compare
     h16550tb6.v            Testbench6 with auto compare
     h16550tb7.v            Testbench7 with auto compare


Sources 
-------
  Texas Instruments 16550 data sheet


Support
-------
   Although every effort has been made to ensure that this core functions
   correctly, if a problem is encountered please contact CAST:
 
      Technical Support Hotline: [phone]
      Fax: [phone]
      E-mail: [e-mail]