reg_32bit.vhd

来自「小巧的频率计数器」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity reg_32bit is
   port(load:in std_logic;
        din:in std_logic_vector(31 downto 0);
        dout:out std_logic_vector(31 downto 0));
end reg_32bit;

architecture behave of reg_32bit is
begin
     process(load,din)
     begin
          if load'event and load='1'  then
                 dout<=din;
          end if;
     end process;
end behave;