frequency_counter_2.map.eqn

小巧的频率计数器

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--D1_dout[0] is reg_32bit:u_reg_32bit|dout[0]
--operation mode is normal

D1_dout[0]_lut_out = B1_counter[0];
D1_dout[0] = DFFEAS(D1_dout[0]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[1] is reg_32bit:u_reg_32bit|dout[1]
--operation mode is normal

D1_dout[1]_lut_out = B1_counter[1];
D1_dout[1] = DFFEAS(D1_dout[1]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[2] is reg_32bit:u_reg_32bit|dout[2]
--operation mode is normal

D1_dout[2]_lut_out = B1_counter[2];
D1_dout[2] = DFFEAS(D1_dout[2]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[3] is reg_32bit:u_reg_32bit|dout[3]
--operation mode is normal

D1_dout[3]_lut_out = B1_counter[3];
D1_dout[3] = DFFEAS(D1_dout[3]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[4] is reg_32bit:u_reg_32bit|dout[4]
--operation mode is normal

D1_dout[4]_lut_out = B2_counter[0];
D1_dout[4] = DFFEAS(D1_dout[4]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[5] is reg_32bit:u_reg_32bit|dout[5]
--operation mode is normal

D1_dout[5]_lut_out = B2_counter[1];
D1_dout[5] = DFFEAS(D1_dout[5]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[6] is reg_32bit:u_reg_32bit|dout[6]
--operation mode is normal

D1_dout[6]_lut_out = B2_counter[2];
D1_dout[6] = DFFEAS(D1_dout[6]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[7] is reg_32bit:u_reg_32bit|dout[7]
--operation mode is normal

D1_dout[7]_lut_out = B2_counter[3];
D1_dout[7] = DFFEAS(D1_dout[7]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[8] is reg_32bit:u_reg_32bit|dout[8]
--operation mode is normal

D1_dout[8]_lut_out = B3_counter[0];
D1_dout[8] = DFFEAS(D1_dout[8]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[9] is reg_32bit:u_reg_32bit|dout[9]
--operation mode is normal

D1_dout[9]_lut_out = B3_counter[1];
D1_dout[9] = DFFEAS(D1_dout[9]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[10] is reg_32bit:u_reg_32bit|dout[10]
--operation mode is normal

D1_dout[10]_lut_out = B3_counter[2];
D1_dout[10] = DFFEAS(D1_dout[10]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[11] is reg_32bit:u_reg_32bit|dout[11]
--operation mode is normal

D1_dout[11]_lut_out = B3_counter[3];
D1_dout[11] = DFFEAS(D1_dout[11]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[12] is reg_32bit:u_reg_32bit|dout[12]
--operation mode is normal

D1_dout[12]_lut_out = B4_counter[0];
D1_dout[12] = DFFEAS(D1_dout[12]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[13] is reg_32bit:u_reg_32bit|dout[13]
--operation mode is normal

D1_dout[13]_lut_out = B4_counter[1];
D1_dout[13] = DFFEAS(D1_dout[13]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[14] is reg_32bit:u_reg_32bit|dout[14]
--operation mode is normal

D1_dout[14]_lut_out = B4_counter[2];
D1_dout[14] = DFFEAS(D1_dout[14]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[15] is reg_32bit:u_reg_32bit|dout[15]
--operation mode is normal

D1_dout[15]_lut_out = B4_counter[3];
D1_dout[15] = DFFEAS(D1_dout[15]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[16] is reg_32bit:u_reg_32bit|dout[16]
--operation mode is normal

D1_dout[16]_lut_out = B5_counter[0];
D1_dout[16] = DFFEAS(D1_dout[16]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[17] is reg_32bit:u_reg_32bit|dout[17]
--operation mode is normal

D1_dout[17]_lut_out = B5_counter[1];
D1_dout[17] = DFFEAS(D1_dout[17]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[18] is reg_32bit:u_reg_32bit|dout[18]
--operation mode is normal

D1_dout[18]_lut_out = B5_counter[2];
D1_dout[18] = DFFEAS(D1_dout[18]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[19] is reg_32bit:u_reg_32bit|dout[19]
--operation mode is normal

D1_dout[19]_lut_out = B5_counter[3];
D1_dout[19] = DFFEAS(D1_dout[19]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[20] is reg_32bit:u_reg_32bit|dout[20]
--operation mode is normal

D1_dout[20]_lut_out = B6_counter[0];
D1_dout[20] = DFFEAS(D1_dout[20]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[21] is reg_32bit:u_reg_32bit|dout[21]
--operation mode is normal

D1_dout[21]_lut_out = B6_counter[1];
D1_dout[21] = DFFEAS(D1_dout[21]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[22] is reg_32bit:u_reg_32bit|dout[22]
--operation mode is normal

D1_dout[22]_lut_out = B6_counter[2];
D1_dout[22] = DFFEAS(D1_dout[22]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[23] is reg_32bit:u_reg_32bit|dout[23]
--operation mode is normal

D1_dout[23]_lut_out = B6_counter[3];
D1_dout[23] = DFFEAS(D1_dout[23]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[24] is reg_32bit:u_reg_32bit|dout[24]
--operation mode is normal

D1_dout[24]_lut_out = B7_counter[0];
D1_dout[24] = DFFEAS(D1_dout[24]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[25] is reg_32bit:u_reg_32bit|dout[25]
--operation mode is normal

D1_dout[25]_lut_out = B7_counter[1];
D1_dout[25] = DFFEAS(D1_dout[25]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[26] is reg_32bit:u_reg_32bit|dout[26]
--operation mode is normal

D1_dout[26]_lut_out = B7_counter[2];
D1_dout[26] = DFFEAS(D1_dout[26]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[27] is reg_32bit:u_reg_32bit|dout[27]
--operation mode is normal

D1_dout[27]_lut_out = B7_counter[3];
D1_dout[27] = DFFEAS(D1_dout[27]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[28] is reg_32bit:u_reg_32bit|dout[28]
--operation mode is normal

D1_dout[28]_lut_out = B8_counter[0];
D1_dout[28] = DFFEAS(D1_dout[28]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[29] is reg_32bit:u_reg_32bit|dout[29]
--operation mode is normal

D1_dout[29]_lut_out = B8_counter[1];
D1_dout[29] = DFFEAS(D1_dout[29]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[30] is reg_32bit:u_reg_32bit|dout[30]
--operation mode is normal

D1_dout[30]_lut_out = B8_counter[2];
D1_dout[30] = DFFEAS(D1_dout[30]_lut_out, !C1_counter_en, VCC, , , , , , );


--D1_dout[31] is reg_32bit:u_reg_32bit|dout[31]
--operation mode is normal

D1_dout[31]_lut_out = B8_counter[3];
D1_dout[31] = DFFEAS(D1_dout[31]_lut_out, !C1_counter_en, VCC, , , , , , );


--B1_counter[0] is counter_10:u0_counter_10|counter[0]
--operation mode is normal

B1_counter[0]_lut_out = !B1_counter[0] & (!B1_counter[1] & !B1_counter[2] # !B1_counter[3]);
B1_counter[0] = DFFEAS(B1_counter[0]_lut_out, fsin, !C1_clr_counter, , C1_counter_en, , , , );


--C1_counter_en is counter_ctrl:u_counter_ctrl|counter_en
--operation mode is normal

C1_counter_en_lut_out = !C1_counter_en;
C1_counter_en = DFFEAS(C1_counter_en_lut_out, clk, VCC, , , , , , );


--B1_counter[1] is counter_10:u0_counter_10|counter[1]
--operation mode is normal

B1_counter[1]_lut_out = !B1_counter[3] & (B1_counter[0] $ B1_counter[1]);
B1_counter[1] = DFFEAS(B1_counter[1]_lut_out, fsin, !C1_clr_counter, , C1_counter_en, , , , );


--B1_counter[2] is counter_10:u0_counter_10|counter[2]
--operation mode is normal

B1_counter[2]_lut_out = !B1_counter[3] & (B1_counter[2] $ (B1_counter[0] & B1_counter[1]));
B1_counter[2] = DFFEAS(B1_counter[2]_lut_out, fsin, !C1_clr_counter, , C1_counter_en, , , , );


--B1_counter[3] is counter_10:u0_counter_10|counter[3]
--operation mode is normal

B1_counter[3]_lut_out = B1_counter[3] & !B1_counter[0] & !B1_counter[1] & !B1_counter[2] # !B1_counter[3] & B1_counter[0] & B1_counter[1] & B1_counter[2];
B1_counter[3] = DFFEAS(B1_counter[3]_lut_out, fsin, !C1_clr_counter, , C1_counter_en, , , , );


--B2_counter[0] is counter_10:u1_counter_10|counter[0]
--operation mode is normal

B2_counter[0]_lut_out = !B2_counter[0] & (!B2_counter[1] & !B2_counter[2] # !B2_counter[3]);
B2_counter[0] = DFFEAS(B2_counter[0]_lut_out, B1L6, !C1_clr_counter, , C1_counter_en, , , , );


--B2_counter[1] is counter_10:u1_counter_10|counter[1]
--operation mode is normal

B2_counter[1]_lut_out = !B2_counter[3] & (B2_counter[0] $ B2_counter[1]);
B2_counter[1] = DFFEAS(B2_counter[1]_lut_out, B1L6, !C1_clr_counter, , C1_counter_en, , , , );


--B2_counter[2] is counter_10:u1_counter_10|counter[2]
--operation mode is normal

B2_counter[2]_lut_out = !B2_counter[3] & (B2_counter[2] $ (B2_counter[0] & B2_counter[1]));
B2_counter[2] = DFFEAS(B2_counter[2]_lut_out, B1L6, !C1_clr_counter, , C1_counter_en, , , , );


--B2_counter[3] is counter_10:u1_counter_10|counter[3]
--operation mode is normal

B2_counter[3]_lut_out = B2_counter[3] & !B2_counter[0] & !B2_counter[1] & !B2_counter[2] # !B2_counter[3] & B2_counter[0] & B2_counter[1] & B2_counter[2];
B2_counter[3] = DFFEAS(B2_counter[3]_lut_out, B1L6, !C1_clr_counter, , C1_counter_en, , , , );


--B3_counter[0] is counter_10:u2_counter_10|counter[0]
--operation mode is normal

B3_counter[0]_lut_out = !B3_counter[0] & (!B3_counter[1] & !B3_counter[2] # !B3_counter[3]);
B3_counter[0] = DFFEAS(B3_counter[0]_lut_out, B2L6, !C1_clr_counter, , C1_counter_en, , , , );


--B3_counter[1] is counter_10:u2_counter_10|counter[1]
--operation mode is normal

B3_counter[1]_lut_out = !B3_counter[3] & (B3_counter[0] $ B3_counter[1]);
B3_counter[1] = DFFEAS(B3_counter[1]_lut_out, B2L6, !C1_clr_counter, , C1_counter_en, , , , );


--B3_counter[2] is counter_10:u2_counter_10|counter[2]
--operation mode is normal

B3_counter[2]_lut_out = !B3_counter[3] & (B3_counter[2] $ (B3_counter[0] & B3_counter[1]));
B3_counter[2] = DFFEAS(B3_counter[2]_lut_out, B2L6, !C1_clr_counter, , C1_counter_en, , , , );


--B3_counter[3] is counter_10:u2_counter_10|counter[3]
--operation mode is normal

B3_counter[3]_lut_out = B3_counter[3] & !B3_counter[0] & !B3_counter[1] & !B3_counter[2] # !B3_counter[3] & B3_counter[0] & B3_counter[1] & B3_counter[2];
B3_counter[3] = DFFEAS(B3_counter[3]_lut_out, B2L6, !C1_clr_counter, , C1_counter_en, , , , );


--B4_counter[0] is counter_10:u3_counter_10|counter[0]
--operation mode is normal

B4_counter[0]_lut_out = !B4_counter[0] & (!B4_counter[1] & !B4_counter[2] # !B4_counter[3]);
B4_counter[0] = DFFEAS(B4_counter[0]_lut_out, B3L6, !C1_clr_counter, , C1_counter_en, , , , );


--B4_counter[1] is counter_10:u3_counter_10|counter[1]
--operation mode is normal

B4_counter[1]_lut_out = !B4_counter[3] & (B4_counter[0] $ B4_counter[1]);
B4_counter[1] = DFFEAS(B4_counter[1]_lut_out, B3L6, !C1_clr_counter, , C1_counter_en, , , , );


--B4_counter[2] is counter_10:u3_counter_10|counter[2]
--operation mode is normal

B4_counter[2]_lut_out = !B4_counter[3] & (B4_counter[2] $ (B4_counter[0] & B4_counter[1]));
B4_counter[2] = DFFEAS(B4_counter[2]_lut_out, B3L6, !C1_clr_counter, , C1_counter_en, , , , );


--B4_counter[3] is counter_10:u3_counter_10|counter[3]
--operation mode is normal

B4_counter[3]_lut_out = B4_counter[3] & !B4_counter[0] & !B4_counter[1] & !B4_counter[2] # !B4_counter[3] & B4_counter[0] & B4_counter[1] & B4_counter[2];
B4_counter[3] = DFFEAS(B4_counter[3]_lut_out, B3L6, !C1_clr_counter, , C1_counter_en, , , , );


--B5_counter[0] is counter_10:u4_counter_10|counter[0]
--operation mode is normal