frequency_counter_2.vhd

小巧的频率计数器

--  这个程序用来测量输入信号的频率
--  重点在于这个程序演示了，如何在顶层设计中调用已经编译好的模块，使用package
--  使用package将编译好的模块封装，以供顶层调用，注意这个程序顶层程序的调用方法


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity frequency_counter_2 is 
      port(fsin:in std_logic;
           clk:in std_logic;
           dout:out std_logic_vector(31 downto 0));
end frequency_counter_2;

architecture frequency_counter_2 of frequency_counter_2 is
    component counter_10
          port(clk:in std_logic;
               clr:in std_logic;
               en: in std_logic;
               counter_out: out std_logic_vector(3 downto 0);
               carry_out: out std_logic);
    end component;
   
    component reg_32bit
          port(load:in std_logic;
               din:in std_logic_vector(31 downto 0);
               dout:out std_logic_vector(31 downto 0));
    end component;

    component counter_ctrl
          port(clk:in std_logic;
               counter_en:out std_logic;
               clr_counter:out std_logic;
               load:out std_logic);
    end component;

    signal counter_en:std_logic;
    signal clr_counter:std_logic;
    signal load:std_logic;
    signal din_reg:std_logic_vector(31 downto 0);
    signal din_0,din_1,din_2,din_3,din_4,din_5,din_6,din_7:std_logic_vector(3 downto 0);
    signal carry_0:std_logic;
    signal carry_1:std_logic;
    signal carry_2:std_logic;
    signal carry_3:std_logic;
    signal carry_4:std_logic;
    signal carry_5:std_logic;
    signal carry_6:std_logic;
    signal carry_7:std_logic;
   


begin
    u_counter_ctrl: counter_ctrl  port map(clk,counter_en,clr_counter,load);
    u_reg_32bit: reg_32bit port map(load,din_reg,dout);
    u0_counter_10: counter_10 port map(fsin,clr_counter,counter_en,din_0,carry_0);
    u1_counter_10: counter_10 port map(carry_0,clr_counter,counter_en,din_1,carry_1);
    u2_counter_10: counter_10 port map(carry_1,clr_counter,counter_en,din_2,carry_2);
    u3_counter_10: counter_10 port map(carry_2,clr_counter,counter_en,din_3,carry_3);
    u4_counter_10: counter_10 port map(carry_3,clr_counter,counter_en,din_4,carry_4);
    u5_counter_10: counter_10 port map(carry_4,clr_counter,counter_en,din_5,carry_5);
    u6_counter_10: counter_10 port map(carry_4,clr_counter,counter_en,din_6,carry_6);
    u7_counter_10: counter_10 port map(carry_6,clr_counter,counter_en,din_7,carry_7);
    din_reg<=din_7&din_6&din_5&din_4&din_3&din_2&din_1&din_0;
end frequency_counter_2;