phasea.vhd

基于VHDL的DDS设计

 -----------------------------------------------------------------------------                                                                     
 -- Project Name         : NCO                                            
 --                                                                             
 -- Author               : Bluetea
 -- Creation Date        : 03/11/04 18:20:21                                              
 -- Version Number       : 1.0                                                                                                                                                                        
 -- Description          :                                                                                                                                  
 -- This block is the phase accumulator of the NCO.  This block will accumulate
 -- a 32 bit phase word with the upper 8 bits representing the actual phase 
 -- table lookup value.  This accumulator is piped in 8 bit steps.  The input to
 -- this block is the synchronous frequency word loaded in the proper pipe order.
 -- The output of this block is an 8 bit quantized phase value or 0 to 2pi
 -----------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY phasea IS
    PORT(
         SYSCLK    : IN  STD_LOGIC;                     -- system clock input
         RESETN    : IN  STD_LOGIC; 			        -- global reset
         SYNCFREQ  : IN  STD_LOGIC_VECTOR (31 DOWNTO 0);-- synchronous frequency word
         COS       : OUT STD_LOGIC;                     -- digital cos output
         SIN       : OUT STD_LOGIC;                     -- digital sin output
         PHASE     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)  -- 8 bit quantized phase output
        );
END phasea;

ARCHITECTURE Accum OF phasea IS
--  four levels of pipeline adders
    SIGNAL pipe1,pipe2,pipe3,pipe4	: STD_LOGIC_VECTOR (7 DOWNTO 0);
--  four levels of pipeline carrys
    SIGNAL pipec0,pipec1,pipec2,pipec3	: STD_LOGIC ;
    
--  8 bit adders of accumulator
    SIGNAL add1,add2,add3,add4	: STD_LOGIC_VECTOR (7 DOWNTO 0);
--  carry outputs of adders
    SIGNAL c1,c2,c3,c4	: STD_LOGIC ;
    
	COMPONENT lpm_add_sub
	GENERIC (
		LPM_WIDTH	          : POSITIVE;
		LPM_DIRECTION         : STRING;
		ONE_INPUT_IS_CONSTANT : STRING
	);
	PORT (
		dataa,datab	 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		overflow     : OUT STD_LOGIC ;
		cin	         : IN STD_LOGIC ;
		result	     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;

BEGIN

	lpm_add_1 : lpm_add_sub
	GENERIC MAP (LPM_WIDTH=>8,LPM_DIRECTION=>"ADD",ONE_INPUT_IS_CONSTANT=>"NO")
	PORT MAP (dataa=>pipe1,datab=>SYNCFREQ(7 DOWNTO 0),cin=>pipec0,overflow=>c1,result=>add1);
	lpm_add_2 : lpm_add_sub
	GENERIC MAP (LPM_WIDTH=>8,LPM_DIRECTION=>"ADD",ONE_INPUT_IS_CONSTANT=>"NO")
	PORT MAP (dataa=>pipe2,datab=>SYNCFREQ(15 DOWNTO 8),cin=>pipec1,overflow=>c2,result=>add2);
	lpm_add_3 : lpm_add_sub
	GENERIC MAP (LPM_WIDTH=>8,LPM_DIRECTION=>"ADD",ONE_INPUT_IS_CONSTANT=>"NO")
	PORT MAP (dataa=>pipe3,datab=>SYNCFREQ(23 DOWNTO 16),cin=>pipec2,overflow=>c3,result=>add3);
	lpm_add_4 : lpm_add_sub
	GENERIC MAP (LPM_WIDTH=>8,LPM_DIRECTION=>"ADD",ONE_INPUT_IS_CONSTANT=>"NO")
	PORT MAP (dataa=>pipe4,datab=>SYNCFREQ(31 DOWNTO 24),cin=>pipec3,overflow=>c4,result=>add4);

       pipec0 <= '0';
       PHASE  <= pipe4;
	   SIN    <= not pipe4(7);
	   COS    <= not (pipe4(7) xor pipe4(6));

    process(SYSCLK,RESETN)
    begin
	  if SYSCLK'event and SYSCLK='1' then
		if RESETN='1' then
			pipe1 <=(others=>'0');
            pipe2 <=(others=>'0');
            pipe3 <=(others=>'0');
            pipe4 <=(others=>'0');
            pipec1<= '0';
			pipec2<= '0';
			pipec3<= '0';
        else
            pipe1 <= add1;
			pipe2 <= add2;
			pipe3 <= add3;
			pipe4 <= add4;
			pipec1 <= c1;
			pipec2 <= c2;
			pipec3 <= c3;
       end if;
     end if; 
	end process;

END Accum;