loadpw.vhd

基于VHDL的DDS设计

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 -- Project Name         : NCO                                            
 --                                                                             
 -- Author               : Bluetea
 -- Creation Date        : 03/11/04 18:20:21                                              
 -- Version Number       : 1.0                                                                                                                                                                        
 -- Description          :                                                                                                                                  
 -- This module will register the phase word and output a synchronous phase
 -- word to the phase modulator
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY loadpw IS
    PORT(
         SYSCLK    : IN  STD_LOGIC;                     -- system clock input
         RESETN    : IN  STD_LOGIC; 			        -- global reset
         PWWRN     : IN  STD_LOGIC; 			        -- low asserted frequency word write strobe
         PHASEWORD : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); -- input phase word from external pins
         SYNCPHSWD : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)  -- synchronous phase word
        );
END loadpw;

ARCHITECTURE Load OF loadpw IS
    SIGNAL pwreg    : STD_LOGIC_VECTOR (7 DOWNTO 0);--  input phase word registered
    SIGNAL phswd	: STD_LOGIC_VECTOR (7 DOWNTO 0);--  PW registered values
    SIGNAL pwwrnm   : STD_LOGIC;                    --  meta-stable phase word write strobe 
    SIGNAL pwwrns   : STD_LOGIC ;                   --  synchronous phase word write strobe
    SIGNAL load     : STD_LOGIC;                    --  synchronous load strobes 

BEGIN
    SYNCPHSWD <= phswd;
-- register the input phase word
Reginphaword:process(PWWRN,RESETN)
    begin
	  if RESETN='1' then
			pwreg  <=(others=>'0');
      else
            pwreg <= PHASEWORD;
      end if; 
end process;

-- get a synchronous load strobe on the rising edge of PWWRN	 
Getstrobe:process(SYSCLK,RESETN)
    begin
      if SYSCLK'event and SYSCLK='1' then
	     if RESETN='1' then
            pwwrnm <= '1';
		    pwwrns <= '1';
		    load   <= '0';
            phswd  <=(others=>'0');
         else 
            pwwrnm <= PWWRN;
            pwwrns <= pwwrnm;	              -- got a synchronous PWWRN
            load   <= (NOT pwwrns) AND pwwrnm;-- 微分电路
               if load ='1' then              -- got rising edge		      
                   phswd <= pwreg;	          
		       else
			      phswd <= phswd;
               end if;
         end if;
      end if; 
end process;

END Load;