sinlup.vhd

基于VHDL的DDS设计

 -----------------------------------------------------------------------------                                                                     
 -- Project Name         : NCO                                            
 --                                                                             
 -- Author               : Bluetea
 -- Creation Date        : 03/11/04 18:20:21                                              
 -- Version Number       : 1.0                                                                                                                                                                        
 -- Description          :                                                                                                                                  
 -- This block takes the phase angle value and outputs the sin wave
 -- value to the DAC.  This module looks up the sin wave values stored
 -- as a 1/4 sin wave in the romtab module.
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY sinlup IS
    PORT(
         SYSCLK    : IN  STD_LOGIC;                     -- system clock input
         RESETN    : IN  STD_LOGIC; 			        -- global reset
         MODPHASE  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); -- modulated phase output
         NCOOUT    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)  -- DAC output of sin wave
        );
END sinlup;

ARCHITECTURE sinlook OF sinlup IS
    SIGNAL phaseadd    : STD_LOGIC_VECTOR (5 DOWNTO 0); --  1/4 wave phase address to ROM table
    SIGNAL qwavesin	   : STD_LOGIC_VECTOR (6 DOWNTO 0); --  1/4 wave sin value from ROM table
    SIGNAL qwavesin_ff : STD_LOGIC_VECTOR (6 DOWNTO 0); --  rom table output registered
    SIGNAL modphase_msb1_ff ,modphase_msb2_ff,modphase_msb3_ff : STD_LOGIC; --  modulated phase MSB
    
    COMPONENT romtab
    PORT(
             SYSCLK    : IN  STD_LOGIC;
             PHASEADD  : IN  STD_LOGIC_VECTOR (5 DOWNTO 0);--phase address value
             QWAVESIN  : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) --1/4 wave sin value
         );
    END COMPONENT;  
 
BEGIN
    U_romtab: romtab  PORT MAP(SYSCLK,phaseadd,qwavesin);
    
-- get the phase angle for 1/4 rom table
 
U_grtphtab:process(SYSCLK,RESETN)
    begin
      if SYSCLK'event and SYSCLK='1' then
	     if RESETN='1' then
            modphase_msb1_ff <= '0';
		    modphase_msb2_ff <= '0';
            phaseadd         <=(others=>'0');
            qwavesin_ff      <=(others=>'0');
            NCOOUT           <=(others=>'0');
         else 
            modphase_msb1_ff <= MODPHASE(7);
   			modphase_msb2_ff <= modphase_msb1_ff;
            modphase_msb3_ff <= modphase_msb2_ff;
            NCOOUT(7)        <= modphase_msb3_ff;
			qwavesin_ff      <= qwavesin;
               if  MODPHASE(6) ='1' then              		      
                   phaseadd <= not MODPHASE(5 DOWNTO 0);     -- 反向查表          
		       else
			       phaseadd <= MODPHASE(5 DOWNTO 0);         -- 正向查表
               end if;
               if modphase_msb3_ff ='1' then              		      
                   NCOOUT(6 DOWNTO 0) <= (not qwavesin_ff)+1;-- 输出补码          
		       else
			       NCOOUT(6 DOWNTO 0) <= qwavesin_ff;        -- 输出原码
               end if;
         end if;
      end if; 
end process;

END sinlook;