📄 clocka.rpt
字号:
- 4 - A 04 DFFE 1 4 0 13 |CLOCK:1|minhigh2 (|CLOCK:1|:54)
- 3 - A 04 DFFE 1 5 0 14 |CLOCK:1|minhigh1 (|CLOCK:1|:55)
- 2 - A 04 DFFE 1 3 0 14 |CLOCK:1|minhigh0 (|CLOCK:1|:56)
- 5 - A 19 DFFE 1 5 0 11 |CLOCK:1|hourlow3 (|CLOCK:1|:57)
- 6 - A 20 DFFE 1 4 0 11 |CLOCK:1|hourlow2 (|CLOCK:1|:58)
- 8 - A 20 DFFE 1 5 0 15 |CLOCK:1|hourlow1 (|CLOCK:1|:59)
- 1 - A 04 DFFE 1 3 0 15 |CLOCK:1|hourlow0 (|CLOCK:1|:60)
- 1 - A 24 DFFE 1 4 0 8 |CLOCK:1|hourhigh1 (|CLOCK:1|:61)
- 2 - A 24 DFFE 1 4 0 8 |CLOCK:1|hourhigh0 (|CLOCK:1|:62)
- 5 - A 04 AND2 s 0 3 0 2 |CLOCK:1|~219~1
- 3 - A 19 AND2 s 0 2 0 3 |CLOCK:1|~219~2
- 4 - A 20 AND2 s 0 3 0 1 |CLOCK:1|~219~3
- 7 - A 20 AND2 s 0 2 0 1 |CLOCK:1|~219~4
- 8 - A 04 AND2 s 0 4 0 1 |CLOCK:1|~219~5
- 7 - A 24 OR2 s 0 4 0 1 |CLOCK:1|~219~6
- 7 - A 22 AND2 0 4 0 12 |CLOCK:1|:219
- 5 - A 25 AND2 0 3 0 6 |CLOCK:1|:235
- 2 - A 21 AND2 0 4 0 5 |CLOCK:1|:251
- 4 - A 26 OR2 ! 0 4 0 3 |CLOCK:1|:292
- 2 - A 19 AND2 s 0 3 0 4 |CLOCK:1|~501~1
- 6 - A 24 OR2 s 0 4 0 2 |CLOCK:1|~513~1
- 2 - A 27 OR2 s 0 3 0 3 |CLOCK:1|~610~1
- 8 - A 13 OR2 0 4 0 1 |CLOCK:1|:726
- 5 - A 05 OR2 0 4 0 1 |CLOCK:1|:732
- 1 - A 05 OR2 0 4 0 1 |CLOCK:1|:738
- 8 - A 07 OR2 0 4 0 1 |CLOCK:1|:884
- 5 - A 07 OR2 0 4 0 1 |CLOCK:1|:890
- 7 - A 04 OR2 s 0 4 0 1 |CLOCK:1|~926~1
- 6 - A 04 OR2 s 0 4 0 1 |CLOCK:1|~932~1
- 3 - A 05 AND2 s ! 0 3 0 6 |CLOCK:1|~938~1
- 6 - A 19 OR2 s 0 4 0 1 |CLOCK:1|~944~1
- 1 - A 19 OR2 s 0 4 0 1 |CLOCK:1|~950~1
- 7 - A 19 OR2 s 0 4 0 1 |CLOCK:1|~956~1
- 7 - A 27 OR2 s 0 3 0 6 |CLOCK:1|~962~1
- 5 - A 27 OR2 s 0 4 0 1 |CLOCK:1|~968~1
- 1 - A 14 DFFE 2 0 0 1 |CONTROL:2|adjsta~1
- 6 - A 14 DFFE 2 1 0 3 |CONTROL:2|adjsta~2
- 5 - A 14 DFFE 2 1 0 4 |CONTROL:2|adjsta~3
- 2 - A 14 DFFE 2 1 0 4 |CONTROL:2|adjsta~4
- 3 - A 14 DFFE 2 1 0 3 |CONTROL:2|adjsta~5
- 7 - A 14 DFFE 2 1 0 5 |CONTROL:2|adjsta~6
- 5 - A 17 AND2 s 0 3 0 3 |CONTROL:2|adjsta~7~2
- 4 - A 14 DFFE 2 2 0 7 |CONTROL:2|adjsta~7
- 3 - A 20 AND2 0 2 0 1 |CONTROL:2|LPM_ADD_SUB:247|addcore:adder|:59
- 5 - A 13 AND2 0 2 0 1 |CONTROL:2|LPM_ADD_SUB:300|addcore:adder|:59
- 4 - A 02 AND2 0 2 0 1 |CONTROL:2|LPM_ADD_SUB:353|addcore:adder|:59
- 8 - A 14 DFFE 2 0 0 20 |CONTROL:2|setmark (|CONTROL:2|:26)
- 5 - A 24 DFFE 2 2 0 1 |CONTROL:2|hourhigh1 (|CONTROL:2|:27)
- 4 - A 24 DFFE 2 1 0 2 |CONTROL:2|hourhigh0 (|CONTROL:2|:28)
- 5 - A 20 DFFE 2 3 0 1 |CONTROL:2|hourlow3 (|CONTROL:2|:29)
- 1 - A 20 DFFE 2 3 0 2 |CONTROL:2|hourlow2 (|CONTROL:2|:30)
- 2 - A 20 DFFE 2 2 0 3 |CONTROL:2|hourlow1 (|CONTROL:2|:31)
- 1 - A 17 DFFE 2 2 0 4 |CONTROL:2|hourlow0 (|CONTROL:2|:32)
- 3 - A 17 DFFE 2 3 0 1 |CONTROL:2|minhigh2 (|CONTROL:2|:33)
- 4 - A 17 DFFE 2 2 0 2 |CONTROL:2|minhigh1 (|CONTROL:2|:34)
- 7 - A 17 DFFE 2 1 0 3 |CONTROL:2|minhigh0 (|CONTROL:2|:35)
- 6 - A 13 DFFE 2 3 0 1 |CONTROL:2|minlow3 (|CONTROL:2|:36)
- 3 - A 13 DFFE 2 3 0 2 |CONTROL:2|minlow2 (|CONTROL:2|:37)
- 4 - A 13 DFFE 2 2 0 3 |CONTROL:2|minlow1 (|CONTROL:2|:38)
- 2 - A 17 DFFE 2 2 0 4 |CONTROL:2|minlow0 (|CONTROL:2|:39)
- 4 - A 07 DFFE 2 3 0 1 |CONTROL:2|sechigh2 (|CONTROL:2|:40)
- 2 - A 07 DFFE 2 2 0 2 |CONTROL:2|sechigh1 (|CONTROL:2|:41)
- 1 - A 07 DFFE 2 1 0 3 |CONTROL:2|sechigh0 (|CONTROL:2|:42)
- 6 - A 02 DFFE 2 3 0 1 |CONTROL:2|seclow3 (|CONTROL:2|:43)
- 2 - A 02 DFFE 2 3 0 2 |CONTROL:2|seclow2 (|CONTROL:2|:44)
- 1 - A 02 DFFE 2 2 0 3 |CONTROL:2|seclow1 (|CONTROL:2|:45)
- 1 - A 01 DFFE 2 3 0 4 |CONTROL:2|seclow0 (|CONTROL:2|:46)
- 8 - A 01 AND2 s ! 0 2 0 3 |CONTROL:2|~453~1
- 7 - A 01 AND2 s ! 0 3 0 3 |CONTROL:2|~453~2
- 3 - A 01 AND2 s ! 0 2 0 3 |CONTROL:2|~516~1
- 6 - A 01 AND2 s ! 0 2 0 3 |CONTROL:2|~600~1
- 8 - A 17 AND2 s ! 0 3 0 3 |CONTROL:2|~663~1
- 6 - A 17 AND2 s ! 0 2 0 3 |CONTROL:2|~747~1
- 6 - A 23 DFFE 1 3 0 5 |DISPLAY:17|CURSTA2 (|DISPLAY:17|:37)
- 4 - A 35 DFFE 1 4 0 6 |DISPLAY:17|CURSTA1 (|DISPLAY:17|:38)
- 5 - A 23 DFFE 1 2 0 6 |DISPLAY:17|CURSTA0 (|DISPLAY:17|:39)
- 8 - A 19 AND2 0 4 0 1 |DISPLAY:17|:1286
- 3 - A 24 OR2 ! 0 4 0 2 |DISPLAY:17|:1334
- 6 - A 26 OR2 ! 0 4 0 2 |DISPLAY:17|:1346
- 3 - A 26 AND2 0 4 0 6 |DISPLAY:17|:1370
- 5 - A 26 OR2 s 0 4 0 2 |DISPLAY:17|~1435~1
- 6 - A 32 AND2 0 3 0 1 |DISPLAY:17|:1435
- 2 - A 26 OR2 0 4 0 1 |DISPLAY:17|:1495
- 8 - A 26 OR2 0 4 0 1 |DISPLAY:17|:1553
- 7 - A 26 OR2 0 4 0 1 |DISPLAY:17|:1585
- 1 - A 27 OR2 s 0 2 0 5 |DISPLAY:17|~1849~1
- 8 - A 27 AND2 0 3 0 5 |DISPLAY:17|:1859
- 3 - A 32 OR2 0 3 0 1 |DISPLAY:17|:1924
- 4 - A 33 OR2 0 3 0 1 |DISPLAY:17|:1984
- 8 - A 25 OR2 0 3 0 1 |DISPLAY:17|:2074
- 4 - A 21 OR2 ! 0 4 0 1 |DISPLAY:17|:2344
- 7 - A 21 OR2 ! 0 4 0 2 |DISPLAY:17|:2356
- 3 - A 21 AND2 0 4 0 3 |DISPLAY:17|:2368
- 1 - A 32 OR2 0 4 0 1 |DISPLAY:17|:2431
- 2 - A 33 OR2 0 4 0 1 |DISPLAY:17|:2491
- 1 - A 21 OR2 0 4 0 1 |DISPLAY:17|:2551
- 2 - A 25 OR2 0 4 0 1 |DISPLAY:17|:2583
- 8 - A 22 OR2 0 3 0 1 |DISPLAY:17|:2980
- 2 - A 22 OR2 0 3 0 1 |DISPLAY:17|:3040
- 3 - A 25 OR2 0 3 0 1 |DISPLAY:17|:3070
- 2 - A 34 AND2 0 4 0 2 |DISPLAY:17|:3342
- 2 - A 30 AND2 0 4 0 3 |DISPLAY:17|:3366
- 5 - A 22 OR2 0 4 0 1 |DISPLAY:17|:3489
- 5 - A 34 OR2 s 0 4 0 2 |DISPLAY:17|~3549~1
- 3 - A 22 OR2 s 0 4 0 1 |DISPLAY:17|~3549~2
- 4 - A 01 OR2 0 4 0 1 |DISPLAY:17|:3581
- 7 - A 23 AND2 0 3 0 9 |DISPLAY:17|:3606
- 8 - A 23 AND2 0 3 0 10 |DISPLAY:17|:3616
- 4 - A 23 AND2 0 3 0 13 |DISPLAY:17|:3626
- 1 - A 23 OR2 ! 0 3 0 11 |DISPLAY:17|:3636
- 2 - A 23 AND2 0 3 0 11 |DISPLAY:17|:3646
- 7 - A 35 AND2 0 4 1 0 |DISPLAY:17|:3651
- 5 - A 35 OR2 0 4 1 0 |DISPLAY:17|:3669
- 2 - A 29 OR2 0 4 0 1 |DISPLAY:17|:3709
- 1 - A 29 OR2 s 0 3 0 1 |DISPLAY:17|~3710~1
- 8 - A 30 OR2 s 0 4 0 2 |DISPLAY:17|~3711~1
- 3 - A 29 OR2 0 4 0 1 |DISPLAY:17|:3712
- 8 - A 21 OR2 s 0 4 0 1 |DISPLAY:17|~3713~1
- 6 - A 29 OR2 0 4 0 1 |DISPLAY:17|:3715
- 5 - A 29 OR2 s 0 3 0 1 |DISPLAY:17|~3716~1
- 8 - A 29 OR2 0 4 0 1 |DISPLAY:17|:3718
- 7 - A 29 OR2 0 3 1 0 |DISPLAY:17|:3721
- 6 - A 22 OR2 0 4 0 1 |DISPLAY:17|:3728
- 4 - A 29 OR2 0 4 0 1 |DISPLAY:17|:3729
- 2 - A 32 OR2 0 4 0 1 |DISPLAY:17|:3730
- 5 - A 32 OR2 0 4 0 1 |DISPLAY:17|:3733
- 7 - A 32 OR2 0 4 0 1 |DISPLAY:17|:3736
- 4 - A 32 OR2 0 4 1 0 |DISPLAY:17|:3739
- 5 - A 01 OR2 s 0 4 0 1 |DISPLAY:17|~3757~1
- 7 - A 25 OR2 s 0 3 0 1 |DISPLAY:17|~3757~2
- 4 - A 27 OR2 s 0 4 0 1 |DISPLAY:17|~3757~3
- 6 - A 21 OR2 s 0 4 0 1 |DISPLAY:17|~3757~4
- 5 - A 21 OR2 s 0 4 0 1 |DISPLAY:17|~3757~5
- 6 - A 27 OR2 s 0 3 0 1 |DISPLAY:17|~3757~6
- 3 - A 27 OR2 s 0 4 0 1 |DISPLAY:17|~3757~7
- 1 - A 26 OR2 s 0 4 0 1 |DISPLAY:17|~3757~8
- 1 - A 31 OR2 s 0 4 0 1 |DISPLAY:17|~3757~9
- 4 - A 31 OR2 0 3 1 0 |DISPLAY:17|:3757
- 4 - A 22 OR2 0 3 0 1 |DISPLAY:17|:3763
- 3 - A 33 OR2 0 3 0 1 |DISPLAY:17|:3766
- 5 - A 33 OR2 0 4 0 1 |DISPLAY:17|:3769
- 6 - A 33 OR2 0 4 0 1 |DISPLAY:17|:3772
- 1 - A 33 OR2 0 4 1 0 |DISPLAY:17|:3775
- 4 - A 34 OR2 0 3 0 1 |DISPLAY:17|:3781
- 7 - A 34 OR2 0 4 0 1 |DISPLAY:17|:3788
- 6 - A 34 OR2 0 4 0 1 |DISPLAY:17|:3789
- 8 - A 34 OR2 0 4 0 1 |DISPLAY:17|:3790
- 1 - A 34 OR2 0 4 1 0 |DISPLAY:17|:3793
- 1 - A 22 OR2 0 4 0 1 |DISPLAY:17|:3799
- 6 - A 35 OR2 0 4 0 1 |DISPLAY:17|:3806
- 1 - A 35 OR2 0 4 0 1 |DISPLAY:17|:3807
- 8 - A 35 OR2 0 4 0 1 |DISPLAY:17|:3808
- 2 - A 35 OR2 0 2 1 0 |DISPLAY:17|:3811
- 4 - A 25 OR2 0 4 0 1 |DISPLAY:17|:3817
- 6 - A 25 OR2 0 4 0 1 |DISPLAY:17|:3820
- 1 - A 25 OR2 0 4 0 1 |DISPLAY:17|:3823
- 5 - A 36 OR2 0 4 0 1 |DISPLAY:17|:3826
- 1 - A 36 OR2 0 4 1 0 |DISPLAY:17|:3829
- 3 - A 35 OR2 0 4 1 1 |DISPLAY:17|:3883
- 3 - A 23 SOFT s ! 1 0 0 3 RESET~1
- 1 - A 30 OR2 0 4 0 2 |RING:18|LPM_ADD_SUB:185|addcore:adder|pcarry2
- 6 - A 28 OR2 0 3 0 1 |RING:18|LPM_ADD_SUB:185|addcore:adder|pcarry3
- 6 - A 30 OR2 0 2 0 1 |RING:18|LPM_ADD_SUB:185|addcore:adder|:115
- 7 - A 30 OR2 0 4 0 1 |RING:18|LPM_ADD_SUB:185|addcore:adder|:116
- 1 - A 28 OR2 0 3 0 1 |RING:18|LPM_ADD_SUB:185|addcore:adder|:117
- 3 - A 34 OR2 0 3 0 1 |RING:18|LPM_MULT:172|multcore:mult_core|:1250
- 5 - A 28 OR2 0 2 0 2 |RING:18|LPM_MULT:172|multcore:mult_core|:1378
- 5 - A 30 AND2 0 1 0 3 |RING:18|LPM_MULT:172|multcore:mult_core|:1402
- 4 - A 30 AND2 0 1 0 2 |RING:18|LPM_MULT:172|multcore:mult_core|:1405
- 3 - A 36 AND2 s 0 3 0 1 |RING:18|~267~1
- 4 - A 36 AND2 s ! 0 4 0 1 |RING:18|~267~2
- 2 - A 28 AND2 s 0 4 0 1 |RING:18|~351~1
- 2 - A 36 OR2 s ! 0 4 0 1 |RING:18|~351~2
- 3 - A 28 AND2 0 4 0 1 |RING:18|:351
- 7 - A 28 AND2 s 0 3 0 1 |RING:18|~1034~1
- 3 - A 30 OR2 s 0 4 0 1 |RING:18|~1034~2
- 8 - A 28 AND2 0 2 0 1 |RING:18|:1034
- 4 - A 28 OR2 1 2 1 0 |RING:18|:1053
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\zhao\vhdl\neweda\clocka.rpt
clocka
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 60/144( 41%) 20/ 72( 27%) 35/ 72( 48%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 3/ 72( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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